| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.td | 382 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), 383 opcodestr, "$rs1, $rs2, $imm12">, 391 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 392 opcodestr, "$rd, ${imm12}(${rs1})">; 400 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12), 401 opcodestr, "$rs2, ${imm12}(${rs1})">; 405 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 406 opcodestr, "$rd, $rs1, $imm12">, 424 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1), 425 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>; [all …]
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| D | RISCVInstrFormats.td | 311 bits<12> imm12; 315 let Inst{31-20} = imm12; 356 bits<12> imm12; 360 let Inst{31-25} = imm12{11-5}; 364 let Inst{11-7} = imm12{4-0}; 371 bits<12> imm12; 375 let Inst{31} = imm12{11}; 376 let Inst{30-25} = imm12{9-4}; 380 let Inst{11-8} = imm12{3-0}; 381 let Inst{7} = imm12{10};
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| D | RISCVInstrInfoD.td | 71 (ins GPR:$rs1, simm12:$imm12), 72 "fld", "$rd, ${imm12}(${rs1})">, 80 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12), 81 "fsd", "$rs2, ${imm12}(${rs1})">,
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| D | RISCVInstrInfoA.td | 68 def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), (vt StTy:$rs2)), 69 (Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>; 70 def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), (vt StTy:$rs2)), 71 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
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| D | RISCVInstrInfoZfh.td | 72 (ins GPR:$rs1, simm12:$imm12), 73 "flh", "$rd, ${imm12}(${rs1})">, 81 (ins FPR16:$rs2, GPR:$rs1, simm12:$imm12), 82 "fsh", "$rs2, ${imm12}(${rs1})">,
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| D | RISCVInstrInfoF.td | 112 (ins GPR:$rs1, simm12:$imm12), 113 "flw", "$rd, ${imm12}(${rs1})">, 121 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 122 "fsw", "$rs2, ${imm12}(${rs1})">,
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| D | RISCVInstrInfoB.td | 567 let imm12 = { 0b01101, 0b0011000 }; 575 let imm12 = { 0b01101, 0b0111000 }; 583 let imm12 = { 0b00101, 0b0000111 };
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 309 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C() local 311 if (bits(imm12, 11, 10) == 0) { in ThumbExpandImm_C() 312 switch (bits(imm12, 9, 8)) { in ThumbExpandImm_C() 332 const uint32_t unrotated_value = 0x80 | bits(imm12, 6, 0); in ThumbExpandImm_C() 333 imm32 = ror(unrotated_value, 32, bits(imm12, 11, 7)); in ThumbExpandImm_C() 352 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12() local 353 return imm12; in ThumbImm12()
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| /freebsd-12-stable/contrib/llvm-project/lld/ELF/Arch/ |
| D | ARM.cpp | 690 int64_t imm12 = val; in relocate() local 692 if (imm12 < 0) { in relocate() 693 imm12 = -imm12; in relocate() 696 checkUInt(loc, imm12, 12, rel); in relocate() 698 write16le(loc + 2, (read16le(loc + 2) & 0xf000) | imm12); in relocate() 813 uint32_t imm12 = read32le(buf) & 0xfff; in getImplicitAddend() local 814 return u ? imm12 : -imm12; in getImplicitAddend() 837 uint64_t imm12 = read16le(buf + 2) & 0x0fff; in getImplicitAddend() local 838 return u ? imm12 : -imm12; in getImplicitAddend()
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| D | RISCV.cpp | 371 uint32_t imm12 = extractBits(val, 12, 12) << 31; in relocate() local 375 insn |= imm12 | imm10_5 | imm4_1 | imm11; in relocate()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| D | CSKYInstrFormats.td | 206 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"), 207 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> { 210 bits<12> imm12; 214 let Inst{11 - 0} = imm12; 219 : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, ${imm12})"), 223 bits<12> imm12; 227 let Inst{11 - 0} = imm12; 234 (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>; 240 (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| D | EmulateInstructionARM64.cpp | 628 const uint32_t imm12 = Bits32(opcode, 21, 10); in EmulateADDSUBImm() local 643 imm = imm12; in EmulateADDSUBImm() 646 imm = imm12 << 12; in EmulateADDSUBImm()
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| /freebsd-12-stable/contrib/binutils/opcodes/ |
| D | arm-dis.c | 3350 unsigned int imm12 = 0; in print_insn_thumb32() local 3351 imm12 |= (given & 0x000000ffu); in print_insn_thumb32() 3352 imm12 |= (given & 0x00007000u) >> 4; in print_insn_thumb32() 3353 imm12 |= (given & 0x04000000u) >> 15; in print_insn_thumb32() 3354 func (stream, "#%u\t; 0x%x", imm12, imm12); in print_insn_thumb32()
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| /freebsd-12-stable/contrib/llvm-project/lld/lib/ReaderWriter/MachO/ |
| D | ArchHandler_arm.cpp | 490 uint32_t imm12 = (instruction & 0x00000FFF); in getWordFromArmMov() local 491 return (imm4 << 12) | imm12; in getWordFromArmMov() 506 uint32_t imm12 = word & 0x0FFF; in setWordFromArmMov() local 507 return (instr & 0xFFF0F000) | (imm4 << 16) | imm12; in setWordFromArmMov()
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| D | ArchHandler_arm64.cpp | 373 uint32_t imm12 = offset << 10; in setImm12() local 374 return (instruction & 0xFFC003FF) | imm12; in setImm12()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 1087 // addrmode_imm12 := reg +/- imm12 2004 let Inst{11-0} = addr{11-0}; // imm12 2035 let Inst{11-0} = addr{11-0}; // imm12 2067 let Inst{11-0} = addr{11-0}; // imm12 2096 let Inst{11-0} = addr{11-0}; // imm12 2275 let Inst{11-0} = addr{11-0}; // imm12 2815 let Inst{11-0} = addr{11-0}; // imm12 2886 // {11-0} imm12/Rm 2904 // {11-0} imm12/Rm 2996 // {11-0} imm12/Rm [all …]
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| D | ARMInstrFormats.td | 798 // {11-0} imm12/Rm 816 // {11-0} imm12/Rm 835 // {13} 1 == Rm, 0 == imm12 837 // {11-0} imm12/Rm
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| D | ARMInstrThumb2.td | 191 // t2addrmode_imm12 := reg + imm12 202 // t2ldrlabel := imm12 1173 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 1265 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 1849 let Inst{11-0} = addr{11-0}; // imm12 1942 let Inst{11-0} = addr{11-0}; // imm12
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| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 1439 uint32_t imm12 = Bits32(opcode, 11, 0); in EmulateMOVRdImm() local 1440 imm32 = (imm4 << 12) | imm12; in EmulateMOVRdImm() 2481 uint32_t imm12; in EmulateSTRRtSP() local 2491 imm12 = Bits32(opcode, 11, 0); in EmulateSTRRtSP() 2509 offset_addr = sp + imm12; in EmulateSTRRtSP() 2511 offset_addr = sp - imm12; in EmulateSTRRtSP()
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