Searched refs:idx_value (Results 1 – 7 of 7) sorted by relevance
158 u32 idx_value; in r200_packet0_check() local162 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()190 track->zb.offset = idx_value; in r200_packet0_check()192 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()203 track->cb[0].offset = idx_value; in r200_packet0_check()205 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()227 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()231 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()274 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()275 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()[all …]
608 u32 idx_value; in r300_packet0_check() local612 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()644 track->cb[i].offset = idx_value; in r300_packet0_check()646 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()657 track->zb.offset = idx_value; in r300_packet0_check()659 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()687 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()688 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); in r300_packet0_check()697 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()707 track->vap_vf_cntl = idx_value; in r300_packet0_check()[all …]
1298 u32 idx_value; in r100_packet3_load_vbpntr() local1318 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()1321 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()1333 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()1344 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()1347 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()1661 u32 idx_value; in r100_packet0_check() local1666 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()1695 track->zb.offset = idx_value; in r100_packet0_check()1697 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()[all …]
1719 u32 idx_value; in r600_packet3_check() local1724 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()1757 (idx_value & 0xfffffff0) + in r600_packet3_check()1798 idx_value + in r600_packet3_check()1840 if (idx_value & 0x10) { in r600_packet3_check()1989 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()2005 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()2025 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()2105 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; in r600_packet3_check()2116 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; in r600_packet3_check()[all …]
1998 u32 idx_value; in evergreen_packet3_check() local2003 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()2036 (idx_value & 0xfffffff0) + in evergreen_packet3_check()2082 idx_value + in evergreen_packet3_check()2109 idx_value + in evergreen_packet3_check()2226 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); in evergreen_packet3_check()2239 if (idx_value & 0x10) { in evergreen_packet3_check()2439 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_packet3_check()2455 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()2475 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; in evergreen_packet3_check()[all …]
639 u32 idx_value = 0; in radeon_get_ib_value() local656 idx_value = ibc->kpage[new_page][pg_offset/4]; in radeon_get_ib_value()657 return idx_value; in radeon_get_ib_value()
2666 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local2718 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()2725 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()2727 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()2740 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()2747 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()2754 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()2774 start_reg = idx_value << 2; in si_vm_packet3_gfx_check()2825 u32 idx_value = ib[idx]; in si_vm_packet3_compute_check() local2861 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()[all …]