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Searched refs:hasAGPRs (Results 1 – 6 of 6) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h155 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()
167 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()
174 bool hasAGPRs(const TargetRegisterClass *RC) const;
178 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
DSIFixSGPRCopies.cpp262 bool IsAGPR = TRI->hasAGPRs(DstRC); in foldVGPRCopyIntoRegSequence()
823 if (AllAGPRUses && numVGPRUses && !TRI->hasAGPRs(RC0)) { in processPHINode()
DSIRegisterInfo.cpp1061 const bool IsAGPR = !ST.hasGFX90AInsts() && hasAGPRs(RC); in buildSpillLoadStore()
2171 bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const { in hasAGPRs() function in SIRegisterInfo
2221 } else if (hasAGPRs(RC)) { in getSubRegClass()
2332 return RC && hasAGPRs(RC); in isAGPR()
2537 if (hasAGPRs(&RC)) in isProperlyAlignedRC()
DGCNRegPressure.cpp79 STI->hasAGPRs(RC) ? in getRegKind()
DSIInstrInfo.cpp895 if (RI.hasAGPRs(RC)) { in copyPhysReg()
898 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(SrcRC)) { in copyPhysReg()
1202 if (RI.hasAGPRs(DstRC)) in getMovOpcode()
1460 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1595 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
3861 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC); in verifyInstruction()
4966 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) && in legalizeOperandsVOP3()
4998 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
5487 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5491 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
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DSILoadStoreOptimizer.cpp924 bool IsAGPR = TRI->hasAGPRs(DataRC); in checkAndPrepareMerge()
994 if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR) in checkAndPrepareMerge()
1595 return TRI->hasAGPRs(getDataRegClass(*CI.I)) in getTargetRegisterClass()