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Searched refs:getVCC (Results 1 – 9 of 9) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h292 MCRegister getVCC() const;
DSIPreEmitPeephole.cpp81 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch()
DSIInsertWaitcnts.cpp1563 TRI->getVCC()) in insertWaitcntInBlock()
1564 .addReg(TRI->getVCC()); in insertWaitcntInBlock()
DSIPeepholeSDWA.cpp1013 SDWAInst.addReg(TRI->getVCC(), RegState::Define); in convertToSDWA()
DSIInstrInfo.cpp6847 User.getOperand(4).setReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
6850 User.getOperand(5).setReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
6880 .addReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
7378 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
7394 ? Register(RI.getVCC()) in getAddNoCarry()
DSIRegisterInfo.cpp2434 MCRegister SIRegisterInfo::getVCC() const { in getVCC() function in SIRegisterInfo
DAMDGPUISelDAGToDAG.cpp2358 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND()
DAMDGPUInstructionSelector.cpp2496 CondPhysReg = TRI.getVCC(); in selectG_BRCOND()
DSIISelLowering.cpp4252 I.addReg(TRI->getVCC(), RegState::Define); in EmitInstrWithCustomInserter()