Searched refs:getTII (Results 1 – 11 of 11) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 260 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyFoldMergeToZext()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert()
60 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
73 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
|
| D | CombinerHelper.cpp | 544 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
1960 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2730 return Builder.getTII().produceSameValue(*I1, *I2, &MRI); in matchEqualDefs()
3290 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3293 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3342 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
3761 if (Builder.getTII().isExtendLikelyToBeFolded(*ExtMI, MRI)) in matchExtendThroughPhis()
3977 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
|
| D | LegalizerHelper.cpp | 641 << MIRBuilder.getTII().getName(Opc) << "\n"); in createMemLibcall()
650 isLibCallInTailPosition(MI, MIRBuilder.getTII(), MRI); in createMemLibcall()
2546 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
3135 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
3181 const auto &TII = MIRBuilder.getTII(); in lower()
5637 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 472 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
|
| D | MipsCallLowering.cpp | 532 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RDFGraph.h | 662 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 256 const TargetInstrInfo &getTII() { in getTII() function
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1851 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
2807 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue()
4302 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
4646 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); in legalizeSBufferLoad()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | RDFGraph.cpp | 227 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()
|