| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 47 unsigned getResNo() const { in getResNo() function 89 return getSDNode() == Other.getSDNode() && getResNo() == Other.getResNo();
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| D | SelectionDAGPrinter.cpp | 68 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget() 135 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
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| D | ScheduleDAGSDNodes.cpp | 122 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency() 237 if (I.getUse().getResNo() != Chain.getResNo()) in ClusterNeighboringLoads() 477 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() 655 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() 747 VRBaseMap.count({L.getSDNode(), L.getResNo()}) == 0) in ProcessSDDbgValues()
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| D | ResourcePriorityQueue.cpp | 135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() 340 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() 490 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
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| D | InstrEmitter.cpp | 118 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg() 128 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg() 130 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg() 237 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters() 728 SDValue V = SDValue(Op.getSDNode(), Op.getResNo()); in AddDbgValueLocationOps() 813 SDValue Op = SDValue(Node, DbgOperand.getResNo()); in EmitDbgInstrRef()
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| D | SelectionDAG.cpp | 571 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands() 580 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands() 3026 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits() 3029 if (Op.getResNo() == 0) in computeKnownBits() 3036 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits() 3039 if (Op.getResNo() == 0) in computeKnownBits() 3074 if (Op.getResNo() != 1) in computeKnownBits() 3240 } else if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits() 3319 if (Op.getResNo() == 1) { in computeKnownBits() 3330 assert(Op.getResNo() == 0 && in computeKnownBits() [all …]
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| D | SelectionDAGAddressAnalysis.cpp | 224 if (LSBase->isIndexed() && Base.getResNo() == IndexResNo) in matchLSNode()
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| D | SelectionDAGDumper.cpp | 852 OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':' << Op.getResNo(); in print() 958 if (unsigned RN = Value.getResNo()) in printOperand()
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| D | LegalizeVectorOps.cpp | 227 return SDValue(Result, Op.getResNo()); in TranslateLegalizeResults() 241 return Results[Op.getResNo()]; in RecursivelyLegalizeResults() 284 return Op.getResNo() ? Tmp.first : Tmp.second; in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 914 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], in getCopyToRegs() 1369 SDDbgOperand::fromNode(N.getNode(), N.getResNo())); in handleDebugValue() 1922 SDValue Val = RetOp.getValue(RetOp.getResNo() + i); in visitRet() 1971 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet() 3359 EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); in visitSelect() 3361 DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); in visitSelect() 3369 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); in visitSelect() 3370 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); in visitSelect() 3373 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); in visitSelect() 3778 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue() [all …]
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| D | ScheduleDAGFast.cpp | 228 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| D | LegalizeTypes.cpp | 94 if (UI.getUse().getResNo() == i) in PerformExpensiveChecks()
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| D | DAGCombiner.cpp | 2607 if (V.getResNo() != 1) in getAsCarry() 2712 N1.getResNo() == 0) in visitADDLikeCommutative() 2974 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1) in combineADDCARRYDiamond() 3065 if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1) in combineCarryDiamond() 3143 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitADDCARRYLike() 5737 N0.getOperand(0).getResNo() == 0) || in visitAND() 5738 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND() 10490 if (UI.getUse().getResNo() != N0.getResNo()) in ExtendUsesToFormExtLoad() 10525 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad() 10985 if (UI.getUse().getResNo() != 0 || User == N0.getNode()) in foldSextSetcc() [all …]
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| D | ScheduleDAGRRList.cpp | 1162 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | DAGISelMatcher.cpp | 362 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl() 365 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
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| D | DAGISelMatcherOpt.cpp | 51 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes() 376 CTM->getResNo() != 0 || in FactorNodes()
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| D | DAGISelMatcherEmitter.cpp | 577 if (cast<CheckTypeMatcher>(N)->getResNo() == 0) { in EmitMatcher() 582 OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo() in EmitMatcher()
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| D | DAGISelMatcher.h | 505 unsigned getResNo() const { return ResNo; } in getResNo() function
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 149 unsigned getResNo() const { return ResNo; } 247 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo(); 308 unsigned getResNo() const { return Val.getResNo(); } 2748 return (Op.getResNo() == 1 &&
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2243 if (N.getResNo() != 0) break; in matchAddressRecursively() 2851 if (UI.getUse().getResNo() != Flags.getResNo()) in onlyUsesZeroFlag() 2861 if (FlagUI.getUse().getResNo() != 1) continue; in onlyUsesZeroFlag() 2887 if (UI.getUse().getResNo() != Flags.getResNo()) in hasNoSignFlagUses() 2897 if (FlagUI.getUse().getResNo() != 1) continue; in hasNoSignFlagUses() 2943 if (UI.getUse().getResNo() != Flags.getResNo()) in hasNoCarryFlagUses() 2956 if (FlagUI.getUse().getResNo() != 1) in hasNoCarryFlagUses() 3000 if (StoredVal.getResNo() != 0) return false; in isFusableLoadOpStorePattern() 3396 Op.getNode()->hasNUsesOfValue(NUses, Op.getResNo()); in matchBitExtract()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/ |
| D | M68kISelLowering.cpp | 1669 if (Op.getResNo() != 0 || NeedOF || NeedCF) { in EmitTest() 1995 if (Op.getResNo() == 1 && in isM68kLogicalCmp() 2001 if (Op.getResNo() == 2 && Opc == M68kISD::UMUL) in isM68kLogicalCmp() 2254 Cond.getOperand(0).getResNo() == 1 && in LowerBRCOND()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2634 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && in getCmp() 2638 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 && in getCmp() 2991 return Res.getValue(Op.getResNo()); in lowerSTRICT_FSETCC() 6025 else if (UI.getUse().getResNo() == 0) in combineLOAD() 6038 Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op); in combineLOAD() 6885 if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, tmp0, tmp1)) { in computeKnownBitsForTargetNode() 6890 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode() 6997 if (Op.getResNo() != 0) in ComputeNumSignBitsForTargetNode()
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| D | SystemZISelDAGToDAG.cpp | 1252 if (StoredVal.getResNo() != 0) in isFusableLoadOpStorePattern()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5017 if (Cond.getResNo() == 1 && in LowerSELECT() 5599 if (Cond.getResNo() == 1 && in LowerBRCOND() 5650 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && in LowerBR_CC() 13089 VecRed.getResNo() != 0 || in PerformADDVecReduce() 14368 Op0.getResNo() == 0 && Op1.getResNo() == 1) in PerformVMOVDRRCombine() 14989 UI.getUse().getResNo() != Addr.getResNo()) in CombineBaseUpdate() 15244 UI.getUse().getResNo() != Addr.getResNo()) in PerformMVEVLDCombine() 15378 if (UI.getUse().getResNo() == NumVecs) in CombineVLDDUP() 15402 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP() 18815 if (Op.getResNo() == 0) { in computeKnownBitsForTargetNode() [all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1824 if (Op.getResNo() == 1) { in computeKnownBitsForTargetNode()
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