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Searched refs:getRegSizeInBits (Results 1 – 25 of 51) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp338 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
346 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
354 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
363 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
372 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
501 TargetRegisterInfo::getRegSizeInBits(Register Reg, in getRegSizeInBits() function in TargetRegisterInfo
520 return getRegSizeInBits(*RC); in getRegSizeInBits()
DImplicitNullChecks.cpp388 unsigned PointerRegSizeInBits = TRI->getRegSizeInBits(PointerReg, MRI); in isSuitableMemoryOp()
392 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
394 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits)) in isSuitableMemoryOp()
425 int32_t RegSizeInBits = TRI->getRegSizeInBits(RegUsedInAddr, MRI); in isSuitableMemoryOp()
DMachineVerifier.cpp1716 SrcSize = TRI->getRegSizeInBits(*SrcRC); in visitMachineInstrBefore()
1720 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in visitMachineInstrBefore()
1726 DstSize = TRI->getRegSizeInBits(*DstRC); in visitMachineInstrBefore()
1730 DstSize = TRI->getRegSizeInBits(DstReg, *MRI); in visitMachineInstrBefore()
1790 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI); in visitMachineInstrBefore()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86RegisterInfo.cpp131 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
138 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
145 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
152 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
166 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
DX86TileConfig.cpp174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
DX86SpeculativeLoadHardening.cpp751 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCFG()
1182 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughIndirectBranches()
1566 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1); in extractPredStateFromSP()
1869 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister()
1917 int Bytes = TRI->getRegSizeInBits(*RC) / 8; in hardenValueInRegister()
2188 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCall()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp387 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
394 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp78 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : in getRegKind()
80 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : in getRegKind()
81 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
DSIRegisterInfo.cpp2158 unsigned Size = getRegSizeInBits(*RC); in hasVGPRs()
2172 unsigned Size = getRegSizeInBits(*RC); in hasAGPRs()
2185 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentVGPRClass()
2193 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentAGPRClass()
2201 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
2342 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
2343 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
2344 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
2515 assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32); in get32BitRegister()
2536 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
[all …]
DSILowerI1Copies.cpp98 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
491 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
701 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
DSIInstrInfo.cpp296 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
300 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
663 ((RI.getRegSizeInBits(*RC) == 16) ^ in copyPhysReg()
664 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) { in copyPhysReg()
665 MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg; in copyPhysReg()
798 const unsigned Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
1024 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
1204 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
1206 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
1208 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
[all …]
DSIInstrInfo.h878 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; in getOpSize()
890 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
DInlineAsmLowering.cpp251 unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI); in buildAnyextOrCopy()
252 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI); in buildAnyextOrCopy()
629 unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in lowerInlineAsm()
DInstructionSelect.cpp259 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) { in runOnMachineFunction()
DRegisterBankInfo.cpp503 return TRI.getRegSizeInBits(*RC); in getSizeInBits()
505 return TRI.getRegSizeInBits(Reg, MRI); in getSizeInBits()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRAsmPrinter.cpp115 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
DAVRFrameLowering.cpp255 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
292 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp875 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
876 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h274 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() function
807 unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonVExtract.cpp161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
339 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()
340 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()
DMipsSEInstrInfo.cpp715 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); in compareOpndSize()
716 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); in compareOpndSize()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVEInstrInfo.cpp253 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { in insertBranch()
261 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { in insertBranch()

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