| /freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| D | DiffEngine.h | 73 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
96 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
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| D | DiffEngine.cpp | 446 return ValA.getOrder() < ValB.getOrder(); in sortTargetValues()
449 return ValA.getOrder() == ValB.getOrder() && ValA.getVal() < ValB.getVal(); in sortTargetValues()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 760 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
971 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
984 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1010 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1032 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| D | SDNodeDbgValue.h | 218 unsigned getOrder() const { return Order; } in getOrder() function
258 unsigned getOrder() const { return Order; } in getOrder() function
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| D | SelectionDAGDumper.cpp | 839 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
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| /freebsd-12-stable/stand/ficl/ |
| D | search.c | 110 static void getOrder(FICL_VM *pVM) in getOrder() function
371 dictAppendWord(dp, "get-order", getOrder, FW_DEFAULT); in ficlCompileSearch()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| D | AllocationOrder.h | 111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| D | RegAllocBase.cpp | 128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| D | RegAllocFast.cpp | 791 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
844 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
975 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1209 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1210 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
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| D | BreakFalseDeps.cpp | 153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| D | RegAllocGreedy.cpp | 1096 for (MCRegister PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1180 unsigned OrderLimit = Order.getOrder().size(); in tryEvict()
1199 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in tryEvict()
1607 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
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| D | CriticalAntiDepBreaker.cpp | 402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| D | AggressiveAntiDepBreaker.cpp | 624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Passes/ |
| D | StandardInstrumentations.cpp | 574 std::vector<std::string>::const_iterator BI = Before.getOrder().begin(); in report()
575 std::vector<std::string>::const_iterator BE = Before.getOrder().end(); in report()
576 std::vector<std::string>::const_iterator AI = After.getOrder().begin(); in report()
577 std::vector<std::string>::const_iterator AE = After.getOrder().end(); in report()
697 CFD.getOrder().emplace_back(B.getName()); in generateFunctionData()
700 Data.getOrder().emplace_back(F.getName()); in generateFunctionData()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Passes/ |
| D | StandardInstrumentations.h | 308 std::vector<std::string> &getOrder() { return Order; } in getOrder() function
309 const std::vector<std::string> &getOrder() const { return Order; } in getOrder() function
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 1042 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1228 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1379 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1392 if (RC.getOrder(oi).empty()) in runTargetDesc()
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| D | CodeGenRegisters.h | 430 ArrayRef<Record*> getOrder(unsigned No = 0) const {
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| D | AsmMatcherEmitter.cpp | 1223 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1299 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1300 RC.getOrder().end())]; in buildRegisterClasses()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMLowOverheadLoops.cpp | 118 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const { in getOrder() function in __anon7ef48f7a0111::PostOrderLoopTraversal
1722 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder(); in Expand()
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| D | CGOpenMPRuntime.h | 559 unsigned getOrder() const { return Order; } in getOrder() function
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/AST/ |
| D | StmtPrinter.cpp | 1687 PrintExpr(Node->getOrder()); in VisitAtomicExpr()
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