| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 216 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
223 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
230 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
238 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
245 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
252 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
259 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
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| D | R600ControlFlowFinalizer.cpp | 279 DstMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
288 SrcMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
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| D | SIRegisterInfo.cpp | 440 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
2520 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
2523 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 188 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
208 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
228 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function in MCRegisterInfo
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 575 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function
577 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVMCInstLower.cpp | 182 Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | CalcSpillWeights.cpp | 74 return TRI.getMatchingSuperReg(CopiedPReg, Sub, rc); in copyHint()
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| D | TwoAddressInstructionPass.cpp | 1423 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB)) in processTiedPairs()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1385 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1404 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1419 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1517 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1535 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1548 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
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| D | A15SDOptimizer.cpp | 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
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| D | ARMBaseInstrInfo.cpp | 1672 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1674 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
4950 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4957 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5261 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3294 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3296 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3320 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3322 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3511 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
3513 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, in copyPhysReg()
3528 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
3530 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, in copyPhysReg()
3545 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
3547 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
[all …]
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| D | AArch64LoadStoreOptimizer.cpp | 1143 IsStoreXReg ? Register(TRI->getMatchingSuperReg( in promoteLoadFromStore()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 88 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); in shortenIIF()
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| D | SystemZInstrInfo.cpp | 799 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), in copyPhysReg()
802 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), in copyPhysReg()
813 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
816 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64), in copyPhysReg()
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| D | SystemZRegisterInfo.cpp | 117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 465 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| D | AVRAsmParser.cpp | 79 return MRI->getMatchingSuperReg(Reg, From, Class); in toDREG()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 771 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
788 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, in convertMIMGInst()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/ |
| D | M68kInstrInfo.cpp | 499 Opd.setReg(getRegisterInfo().getMatchingSuperReg( in ExpandCCR()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 606 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 3532 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, in copyPhysReg()
3534 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, in copyPhysReg()
3547 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, in copyPhysReg()
3549 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, in copyPhysReg()
4679 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass); in expandNOVLXLoad()
4702 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass); in expandNOVLXStore()
4769 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in expandPostRAPseudo()
4789 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in expandPostRAPseudo()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 273 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( in printInst()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 1410 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()
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