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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp64 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF); in ResourcePriorityQueue()
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
334 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
345 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
365 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
369 if ((RegPressure[RC->getID()] + in regPressureDelta()
370 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
371 (RegPressure[RC->getID()] + in regPressureDelta()
372 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
[all …]
/freebsd-12-stable/contrib/llvm-project/clang/lib/Frontend/
DTextDiagnosticPrinter.cpp58 if (Info.getID() == diag::fatal_too_many_errors) { in printDiagnosticOptions()
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) && in printDiagnosticOptions()
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) { in printDiagnosticOptions()
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID()); in printDiagnosticOptions()
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID()); in printDiagnosticOptions()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp63 return ContainedRegClasses.test(RC.getID()); in covers()
76 assert((OtherRB.getID() != getID() || &OtherRB == this) && in operator ==()
92 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n" in print()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp588 << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); in SchedulingCost()
597 if (Q.getID() == TopQID) { in SchedulingCost()
640 if (Q.getID() == TopQID) { in SchedulingCost()
676 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 && in SchedulingCost()
692 if (Q.getID() == TopQID && in SchedulingCost()
696 } else if (Q.getID() == BotQID && in SchedulingCost()
705 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) { in SchedulingCost()
714 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { in SchedulingCost()
731 if (Q.getID() == TopQID) { in SchedulingCost()
798 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) in pickNodeFromQueue()
[all …]
DHexagonRegisterInfo.cpp92 switch (RC->getID()) { in getCallerSavedRegs()
357 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
359 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
428 switch (RC.getID()) { in getHexagonSubRegIndex()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
[all …]
/freebsd-12-stable/contrib/llvm-project/lld/lib/Driver/
DDarwinLdDriver.cpp345 switch (kind->getOption().getID()) { in parse()
402 switch (minOS->getOption().getID()) { in parse()
707 if (mod->getOption().getID() == OPT_multi_module) in parse()
737 (pie->getOption().getID() == OPT_pie)) { in parse()
744 (pie->getOption().getID() == OPT_pie)) { in parse()
750 if (pie->getOption().getID() == OPT_no_pie) { in parse()
758 ctx.setPIE(pie->getOption().getID() == OPT_pie); in parse()
780 flagOn = arg->getOption().getID() == OPT_version_load_command; in parse()
781 flagOff = arg->getOption().getID() == OPT_no_version_load_command; in parse()
828 flagOn = arg->getOption().getID() == OPT_function_starts; in parse()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.cpp519 unsigned PredID = Pred->getID(); in addPred()
523 if (PredID == P->getID()) in addPred()
531 return PredID == S.first->getID(); in addPred()
538 unsigned SuccID = Succ->getID(); in addSucc()
542 if (SuccID == S.first->getID()) { in addSucc()
554 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) && in addSucc()
630 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID; in isSUInBlock()
1287 if (!--TopDownBlock2Index[Pred->getID()]) in topologicalSort()
1288 WorkList.push_back(Pred->getID()); in topologicalSort()
1297 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()] && in topologicalSort()
[all …]
DAMDGPUInstructionSelector.cpp88 return RB->getID() == AMDGPU::VCCRegBankID; in isVCC()
284 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
285 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
288 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR()
311 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; in selectG_ADD_SUB()
600 if (DstBank->getID() != AMDGPU::SGPRRegBankID) in selectG_BUILD_VECTOR_TRUNC()
764 assert(RBI.getRegBank(DstReg, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID && in selectG_SBFX_UBFX()
1162 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectRelocConstant()
1184 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize()
1352 if (OffsetRB->getID() != AMDGPU::SGPRRegBankID) in selectDSGWSIntrinsic()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Option/
DOptSpecifier.h29 unsigned getID() const { return ID; } in getID() function
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Option/
DOption.cpp100 if (getID() == Opt.getID()) in matches()
242 if (getID() == UnaliasedOption.getID()) in accept()
DArgList.cpp40 OptRanges.insert(std::make_pair(O.getID(), emptyRange())).first->second; in append()
54 OptRanges.erase(Id.getID()); in eraseArg()
61 auto I = OptRanges.find(Id.getID()); in getRange()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
245 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
246 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
281 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
282 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
405 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
408 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
411 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
413 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
[all …]
/freebsd-12-stable/contrib/llvm-project/lld/MachO/
DDriver.cpp71 switch (outputArg->getOption().getID()) { in getOutputType()
208 switch (arg->getOption().getID()) { in getLTOCachePolicy()
432 switch (arg->getOption().getID()) { in parseLCLinkerOption()
773 if (opt.getGroup().getID() == OPT_grp_deprecated) { in warnIfDeprecatedOption()
782 switch (opt.getGroup().getID()) { in warnIfUnimplementedOption()
993 switch (opt.getID()) { in createFiles()
1024 addLibrary(arg->getValue(), opt.getID() == OPT_needed_l, in createFiles()
1025 opt.getID() == OPT_weak_l, opt.getID() == OPT_reexport_l, in createFiles()
1032 addFramework(arg->getValue(), opt.getID() == OPT_needed_framework, in createFiles()
1033 opt.getID() == OPT_weak_framework, in createFiles()
[all …]
DDriverUtils.cpp63 if (arg->getOption().getID() == OPT_color_diagnostics) { in handleColorDiagnostics()
65 } else if (arg->getOption().getID() == OPT_no_color_diagnostics) { in handleColorDiagnostics()
138 switch (arg->getOption().getID()) { in createResponseFile()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
DMemorySSA.h219 inline unsigned getID() const;
342 OptimizedID = DMA->getID();
347 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
402 OptimizedID = MA->getID();
410 return getOptimized() && OptimizedID == getOptimized()->getID();
420 unsigned getID() const { return ID; }
640 unsigned getID() const { return ID; }
669 inline unsigned MemoryAccess::getID() const {
673 return MD->getID();
674 return cast<MemoryPhi>(this)->getID();
/freebsd-12-stable/contrib/llvm-project/clang/lib/ARCMigrate/
DTransProtectedScope.cpp120 if (I->getID() == diag::err_switch_into_protected_scope && in ProtectedScopeFixer()
133 assert(DiagI->getID() == diag::err_switch_into_protected_scope); in handleProtectedScopeError()
159 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation()); in handleProtectedNote()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h69 unsigned getID() const { return MC->getID(); } in getID() function
125 unsigned ID = RC->getID(); in hasSubClassEq()
720 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
1234 bool isValid() const { return getID() != NumRegClasses; } in isValid()
1237 unsigned getID() const { return ID; } in getID() function
DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID() function
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID() function
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID() function
/freebsd-12-stable/contrib/llvm-project/lld/ELF/
DDriverUtils.cpp62 if (arg->getOption().getID() == OPT_color_diagnostics) { in handleColorDiagnostics()
64 } else if (arg->getOption().getID() == OPT_no_color_diagnostics) { in handleColorDiagnostics()
176 switch (arg->getOption().getID()) { in createResponseFile()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DRegisterBankInfo.h231 unsigned getID() const { return ID; } in getID() function
255 return getID() != InvalidMappingID && OperandsMapping; in isValid()
717 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) in applyMapping()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64RegisterBankInfo.cpp237 switch (RC.getID()) { in getRegBankFromRegClass()
391 assert((OpdMapper.getInstrMapping().getID() >= 1 && in applyMappingImpl()
392 OpdMapper.getInstrMapping().getID() <= 4) && in applyMappingImpl()
635 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
654 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
DAArch64InstructionSelector.cpp486 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
498 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
518 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
581 switch (RB.getID()) { in getMinSizeForRegBank()
845 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) && in isValidCopy()
1018 assert(SrcRegBank.getID() == AArch64::GPRRegBankID); in selectCopy()
1107 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1108 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1117 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1512 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DDAGISelEmitter.cpp118 return LHS->getID() < RHS->getID(); in operator ()()
/freebsd-12-stable/contrib/llvm-project/clang/lib/Analysis/
DProgramPoint.cpp73 Out << RS->getID(Context) << ", \"stmt\": "; in printJson()
191 << "\", \"stmt_id\": " << S->getID(Context) in printJson()

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