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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td18 !strconcat("f32.", !strconcat(name, "\t$dst, $src")),
19 !strconcat("f32.", name), f32Inst>;
29 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
30 !strconcat("f32.", name), f32Inst>;
39 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
40 !strconcat("f32.", name), f32Inst>;
76 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
89 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
90 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
91 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
[all …]
DWebAssemblyInstrConv.td185 "f32.convert_i32_s\t$dst, $src", "f32.convert_i32_s",
189 "f32.convert_i32_u\t$dst, $src", "f32.convert_i32_u",
201 "f32.convert_i64_s\t$dst, $src", "f32.convert_i64_s",
205 "f32.convert_i64_u\t$dst, $src", "f32.convert_i64_u",
222 "f32.demote_f64\t$dst, $src", "f32.demote_f64",
231 "f32.reinterpret_i32\t$dst, $src",
232 "f32.reinterpret_i32", 0xbe>;
/freebsd-12-stable/lib/libc/arm/aeabi/
Daeabi_vfp_float.S39 vcmp.f32 s0, s1
47 vcmpe.f32 s0, s1
55 vcmpe.f32 s1, s0
63 vcmp.f32 s0, s1
74 vcmp.f32 s0, s1
85 vcmp.f32 s0, s1
96 vcmp.f32 s0, s1
107 vcmp.f32 s0, s1
118 vcmp.f32 s0, s1
135 vcvt.s32.f32 s0, s0
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
DVecFuncs.def33 TLI_DEFINE_VECFUNC("llvm.fabs.f32", "vfabsf", FIXED(4))
36 TLI_DEFINE_VECFUNC("llvm.sqrt.f32", "vsqrtf", FIXED(4))
40 TLI_DEFINE_VECFUNC("llvm.exp.f32", "vexpf", FIXED(4))
43 TLI_DEFINE_VECFUNC("llvm.log.f32", "vlogf", FIXED(4))
46 TLI_DEFINE_VECFUNC("llvm.log10.f32", "vlog10f", FIXED(4))
51 TLI_DEFINE_VECFUNC("llvm.sin.f32", "vsinf", FIXED(4))
53 TLI_DEFINE_VECFUNC("llvm.cos.f32", "vcosf", FIXED(4))
74 TLI_DEFINE_VECFUNC("llvm.exp.f32", "_simd_exp_f4", FIXED(4))
90 TLI_DEFINE_VECFUNC("llvm.cos.f32", "_simd_cos_f4", FIXED(4))
95 TLI_DEFINE_VECFUNC("llvm.sin.f32", "_simd_sin_f4", FIXED(4))
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DR600Instructions.td402 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
403 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
404 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
697 [(set f32:$dst, (fabs f32:$src0))]
704 [(set f32:$dst, (fneg f32:$src0))]
754 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
759 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
764 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
769 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
774 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
[all …]
DR600RegisterInfo.td152 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
DSIInstructions.td40 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
66 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
76 [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
798 (int_amdgcn_kill (i1 (setcc f32:$src, InlineImmFP32:$imm, cond:$cond))),
830 //defm : RsqPat<V_RSQ_F32_e32, f32>;
832 def : RsqPat<V_RSQ_F32_e32, f32>;
836 (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
837 (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
853 (f32 (f16_to_fp i32:$src0)),
858 (f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
[all …]
DAMDGPUCallingConv.td23 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
30 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
37 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
46 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
55 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
78 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
88 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
121 CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
208 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
213 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
[all …]
DR600ISelLowering.cpp31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
98 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
99 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
100 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
101 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
102 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
103 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
104 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
105 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
106 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td785 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>;
794 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;
803 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;
812 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;
1048 [(set f32:$XT, (fpimm0))]>;
1131 [(set f32:$XT, (load XForm:$src))]>;
1154 [(store f32:$XT, XForm:$dst)]>;
1167 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>;
1171 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>;
1177 [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>;
[all …]
DPPCInstrSPE.td154 [(set f64:$RT, (any_fpextend f32:$RB))]>;
249 [(set f32:$RT, (fabs f32:$RA))]>;
253 [(set f32:$RT, (any_fadd f32:$RA, f32:$RB))]>;
257 [(set f32:$RT, (any_fpround f64:$RB))]>;
264 [(set f32:$RT, (any_sint_to_fp i32:$RB))]>;
271 [(set f32:$RT, (any_uint_to_fp i32:$RB))]>;
291 [(set i32:$RT, (any_fp_to_sint f32:$RB))]>;
302 [(set i32:$RT, (any_fp_to_uint f32:$RB))]>;
306 [(set f32:$RT, (any_fdiv f32:$RA, f32:$RB))]>;
310 [(set f32:$RT, (any_fmul f32:$RA, f32:$RB))]>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td31 def f32 : ValueType<32, 10>; // 32-bit floating point value
78 def v6i32 : ValueType<192, 53>; // 6 x f32 vector value
79 def v7i32 : ValueType<224, 54>; // 7 x f32 vector value
124 def v1f32 : ValueType<32, 94>; // 1 x f32 vector value
125 def v2f32 : ValueType<64, 95>; // 2 x f32 vector value
126 def v3f32 : ValueType<96, 96>; // 3 x f32 vector value
127 def v4f32 : ValueType<128, 97>; // 4 x f32 vector value
128 def v5f32 : ValueType<160, 98>; // 5 x f32 vector value
129 def v6f32 : ValueType<192, 99>; // 6 x f32 vector value
130 def v7f32 : ValueType<224, 100>; // 7 x f32 vector value
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/
DIntrinsicsNVVM.td32 // * llvm.nvvm.h2f --> llvm.convert.to.fp16.f32
62 !eq(gft,"m16n8k8:c:f32") : !listsplat(llvm_float_ty, 4),
63 !eq(gft,"m16n8k8:d:f32") : !listsplat(llvm_float_ty, 4),
68 !eq(gft,"m16n8k16:c:f32") : !listsplat(llvm_float_ty, 4),
69 !eq(gft,"m16n8k16:d:f32") : !listsplat(llvm_float_ty, 4),
70 !eq(gft,"m16n8k4:c:f32") : !listsplat(llvm_float_ty, 4),
71 !eq(gft,"m16n8k4:d:f32") : !listsplat(llvm_float_ty, 4),
74 // All other supported geometries use the same fragment format for f32 and
80 !eq(ft,"c:f32") : !listsplat(llvm_float_ty, 8),
81 !eq(ft,"d:f32") : !listsplat(llvm_float_ty, 8),
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td19 def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;
63 def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{
76 def vfp_f32imm : Operand<f32>,
77 PatLeaf<(f32 fpimm), [{
413 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
463 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
484 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
507 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
532 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
[all …]
DARMInstrCDE.td548 def : Pat<(f32 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
549 (f32 (CDE_VCX1_fpsp p_imm:$coproc, imm_11b:$imm))>;
550 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)),
551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsCallingConv.td86 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
104 // f32 are returned in registers F0, F2
105 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
151 // f32 arguments are passed in single precision FP registers.
152 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
164 CCIfType<[f32], CCAssignToStack<4, 8>>,
178 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
184 CCIfType<[f32], CCAssignToStack<4, 8>>,
189 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
213 // f32 are returned in registers F0, F2
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td141 !eq(reg, "f32"): Float32Regs);
178 foreach regclass = ["i32", "f32"] in {
586 def INT_NVVM_FMIN_F : F_MATH_2<"min.f32 \t$dst, $src0, $src1;", Float32Regs,
588 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
591 def INT_NVVM_FMAX_F : F_MATH_2<"max.f32 \t$dst, $src0, $src1;", Float32Regs,
593 def INT_NVVM_FMAX_FTZ_F : F_MATH_2<"max.ftz.f32 \t$dst, $src0, $src1;",
616 def INT_NVVM_MUL_RN_FTZ_F : F_MATH_2<"mul.rn.ftz.f32 \t$dst, $src0, $src1;",
618 def INT_NVVM_MUL_RN_F : F_MATH_2<"mul.rn.f32 \t$dst, $src0, $src1;",
620 def INT_NVVM_MUL_RZ_FTZ_F : F_MATH_2<"mul.rz.ftz.f32 \t$dst, $src0, $src1;",
622 def INT_NVVM_MUL_RZ_F : F_MATH_2<"mul.rz.f32 \t$dst, $src0, $src1;",
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVEInstrInfo.td1015 defm LDU : LOADm<"ldu", 0x02, F32, f32, load>;
1073 defm STU : STOREm<"stu", 0x12, F32, f32, store>;
1100 defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>;
1303 let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>;
1359 defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>;
1364 defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;
1369 defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>;
1374 defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
1379 defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, null_frag, simm7fp, mimmfp32>;
1386 defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DSparcCallingConv.td20 // i32 f32 arguments get passed in integer registers if there is space.
21 CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
35 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
115 CCIfInReg<CCIfType<[i32, f32], CCCustom<"CC_Sparc64_Half">>>,
126 // A single f32 return value always goes in %f0. The ABI doesn't specify what
127 // happens to multiple f32 return values outside a struct.
128 CCIfType<[f32], CCCustom<"CC_Sparc64_Half">>,
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/builtins/arm/
Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
Dfloatsisfvfp.S23 vcvt.f32.s32 s0, s0
26 vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15
Dfixunssfsivfp.S23 vcvt.u32.f32 s0, s0
27 vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15
Dfixsfsivfp.S22 vcvt.s32.f32 s0, s0
26 vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15
Daddsf3vfp.S21 vadd.f32 s0, s0, s1
25 vadd.f32 s14, s14, s15

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