Searched refs:div_mask (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12-stable/sys/arm/freescale/vybrid/ |
| D | vf_ccm.c | 159 uint32_t div_mask; member
171 .div_mask = IPG_CLK_DIV_MASK,
195 .div_mask = PLL4_CLK_DIV_MASK,
207 .div_mask = SAI3_DIV_MASK,
219 .div_mask = CKO1_DIV_MASK,
231 .div_mask = ESDHC0_DIV_M,
243 .div_mask = ESDHC1_DIV_M,
255 .div_mask = 0,
267 .div_mask = 0x7,
279 .div_mask = 0,
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| /freebsd-12-stable/sys/arm64/rockchip/clk/ |
| D | rk_clk_composite.c | 54 uint32_t div_mask; member
214 div = ((reg & sc->div_mask) >> sc->div_shift); in rk_clk_composite_recalc()
237 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); in rk_clk_composite_find_best()
311 dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask, in rk_clk_composite_set_freq()
316 val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT; in rk_clk_composite_set_freq()
361 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_composite_register()
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| D | rk_clk_armclk.c | 52 uint32_t div_mask; member
138 div = ((reg & sc->div_mask) >> sc->div_shift) + 1; in rk_clk_armclk_recalc()
200 val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_freq()
245 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_armclk_register()
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| /freebsd-12-stable/sys/arm/nvidia/tegra124/ |
| D | tegra124_clk_per.c | 67 uint32_t div_mask; member
530 uint32_t div_mask; member
570 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
667 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
691 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()
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