Searched refs:cayman (Results 1 – 10 of 10) sorted by relevance
481 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()482 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()483 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()484 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()485 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()486 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()487 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()488 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()489 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()490 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()[all …]
259 value = rdev->config.cayman.tile_config; in radeon_info_ioctl()301 value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()302 rdev->config.cayman.max_shader_engines; in radeon_info_ioctl()317 value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()335 value = rdev->config.cayman.backend_map; in radeon_info_ioctl()362 value = rdev->config.cayman.max_pipes_per_simd; in radeon_info_ioctl()377 value = rdev->config.cayman.max_shader_engines; in radeon_info_ioctl()
1457 struct cayman_asic cayman; member
1153 tmp = rdev->config.cayman.tile_config; in dce4_crtc_do_set_base()
2771 tmp = p->rdev->config.cayman.tile_config; in evergreen_cs_parse()
55 ${REG_DEST_DIR}/cayman_reg_safe.h: ${REG_SRCS_DIR}/cayman ${MKREGTABLE}56 ./${MKREGTABLE} ${REG_SRCS_DIR}/cayman > $@
9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction10 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
140 def : Processor<"cayman", R600_VLIW4_Itin,
1 cayman 0x9400
32079 cayman