1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/12/sys/dev/mlx5/mlx5_ifc.h 365406 2020-09-07 10:35:22Z kib $ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 }; 67 68 enum { 69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 74 }; 75 76 enum { 77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 78 }; 79 80 enum { 81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 83 }; 84 85 enum { 86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 88 MLX5_CMD_OP_INIT_HCA = 0x102, 89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 90 MLX5_CMD_OP_ENABLE_HCA = 0x104, 91 MLX5_CMD_OP_DISABLE_HCA = 0x105, 92 MLX5_CMD_OP_QUERY_PAGES = 0x107, 93 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 94 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 95 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 96 MLX5_CMD_OP_SET_ISSI = 0x10b, 97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 100 MLX5_CMD_OP_CREATE_MKEY = 0x200, 101 MLX5_CMD_OP_QUERY_MKEY = 0x201, 102 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 105 MLX5_CMD_OP_CREATE_EQ = 0x301, 106 MLX5_CMD_OP_DESTROY_EQ = 0x302, 107 MLX5_CMD_OP_QUERY_EQ = 0x303, 108 MLX5_CMD_OP_GEN_EQE = 0x304, 109 MLX5_CMD_OP_CREATE_CQ = 0x400, 110 MLX5_CMD_OP_DESTROY_CQ = 0x401, 111 MLX5_CMD_OP_QUERY_CQ = 0x402, 112 MLX5_CMD_OP_MODIFY_CQ = 0x403, 113 MLX5_CMD_OP_CREATE_QP = 0x500, 114 MLX5_CMD_OP_DESTROY_QP = 0x501, 115 MLX5_CMD_OP_RST2INIT_QP = 0x502, 116 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 117 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 118 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 120 MLX5_CMD_OP_2ERR_QP = 0x507, 121 MLX5_CMD_OP_2RST_QP = 0x50a, 122 MLX5_CMD_OP_QUERY_QP = 0x50b, 123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 125 MLX5_CMD_OP_CREATE_PSV = 0x600, 126 MLX5_CMD_OP_DESTROY_PSV = 0x601, 127 MLX5_CMD_OP_CREATE_SRQ = 0x700, 128 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 129 MLX5_CMD_OP_QUERY_SRQ = 0x702, 130 MLX5_CMD_OP_ARM_RQ = 0x703, 131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 135 MLX5_CMD_OP_CREATE_DCT = 0x710, 136 MLX5_CMD_OP_DESTROY_DCT = 0x711, 137 MLX5_CMD_OP_DRAIN_DCT = 0x712, 138 MLX5_CMD_OP_QUERY_DCT = 0x713, 139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 154 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 155 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 156 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 157 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 158 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 159 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 160 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 161 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 162 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 163 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 164 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 165 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 166 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 167 MLX5_CMD_OP_ALLOC_PD = 0x800, 168 MLX5_CMD_OP_DEALLOC_PD = 0x801, 169 MLX5_CMD_OP_ALLOC_UAR = 0x802, 170 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 171 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 172 MLX5_CMD_OP_ACCESS_REG = 0x805, 173 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 174 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 175 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 176 MLX5_CMD_OP_MAD_IFC = 0x50d, 177 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 178 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 179 MLX5_CMD_OP_NOP = 0x80d, 180 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 181 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 182 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 183 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 184 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 185 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 188 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 189 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 190 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 191 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 192 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 193 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 194 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 195 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 196 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 197 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 198 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 199 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 200 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 201 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 202 MLX5_CMD_OP_CREATE_LAG = 0x840, 203 MLX5_CMD_OP_MODIFY_LAG = 0x841, 204 MLX5_CMD_OP_QUERY_LAG = 0x842, 205 MLX5_CMD_OP_DESTROY_LAG = 0x843, 206 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 207 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 208 MLX5_CMD_OP_CREATE_TIR = 0x900, 209 MLX5_CMD_OP_MODIFY_TIR = 0x901, 210 MLX5_CMD_OP_DESTROY_TIR = 0x902, 211 MLX5_CMD_OP_QUERY_TIR = 0x903, 212 MLX5_CMD_OP_CREATE_SQ = 0x904, 213 MLX5_CMD_OP_MODIFY_SQ = 0x905, 214 MLX5_CMD_OP_DESTROY_SQ = 0x906, 215 MLX5_CMD_OP_QUERY_SQ = 0x907, 216 MLX5_CMD_OP_CREATE_RQ = 0x908, 217 MLX5_CMD_OP_MODIFY_RQ = 0x909, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 225 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 226 MLX5_CMD_OP_CREATE_TIS = 0x912, 227 MLX5_CMD_OP_MODIFY_TIS = 0x913, 228 MLX5_CMD_OP_DESTROY_TIS = 0x914, 229 MLX5_CMD_OP_QUERY_TIS = 0x915, 230 MLX5_CMD_OP_CREATE_RQT = 0x916, 231 MLX5_CMD_OP_MODIFY_RQT = 0x917, 232 MLX5_CMD_OP_DESTROY_RQT = 0x918, 233 MLX5_CMD_OP_QUERY_RQT = 0x919, 234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 248 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 249 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 250 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 251 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 252 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 253 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 254 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 255 }; 256 257 enum { 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 260 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 261 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 262 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 263 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 264 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 270 }; 271 272 struct mlx5_ifc_flow_table_fields_supported_bits { 273 u8 outer_dmac[0x1]; 274 u8 outer_smac[0x1]; 275 u8 outer_ether_type[0x1]; 276 u8 reserved_0[0x1]; 277 u8 outer_first_prio[0x1]; 278 u8 outer_first_cfi[0x1]; 279 u8 outer_first_vid[0x1]; 280 u8 reserved_1[0x1]; 281 u8 outer_second_prio[0x1]; 282 u8 outer_second_cfi[0x1]; 283 u8 outer_second_vid[0x1]; 284 u8 outer_ipv6_flow_label[0x1]; 285 u8 outer_sip[0x1]; 286 u8 outer_dip[0x1]; 287 u8 outer_frag[0x1]; 288 u8 outer_ip_protocol[0x1]; 289 u8 outer_ip_ecn[0x1]; 290 u8 outer_ip_dscp[0x1]; 291 u8 outer_udp_sport[0x1]; 292 u8 outer_udp_dport[0x1]; 293 u8 outer_tcp_sport[0x1]; 294 u8 outer_tcp_dport[0x1]; 295 u8 outer_tcp_flags[0x1]; 296 u8 outer_gre_protocol[0x1]; 297 u8 outer_gre_key[0x1]; 298 u8 outer_vxlan_vni[0x1]; 299 u8 outer_geneve_vni[0x1]; 300 u8 outer_geneve_oam[0x1]; 301 u8 outer_geneve_protocol_type[0x1]; 302 u8 outer_geneve_opt_len[0x1]; 303 u8 reserved_2[0x1]; 304 u8 source_eswitch_port[0x1]; 305 306 u8 inner_dmac[0x1]; 307 u8 inner_smac[0x1]; 308 u8 inner_ether_type[0x1]; 309 u8 reserved_3[0x1]; 310 u8 inner_first_prio[0x1]; 311 u8 inner_first_cfi[0x1]; 312 u8 inner_first_vid[0x1]; 313 u8 reserved_4[0x1]; 314 u8 inner_second_prio[0x1]; 315 u8 inner_second_cfi[0x1]; 316 u8 inner_second_vid[0x1]; 317 u8 inner_ipv6_flow_label[0x1]; 318 u8 inner_sip[0x1]; 319 u8 inner_dip[0x1]; 320 u8 inner_frag[0x1]; 321 u8 inner_ip_protocol[0x1]; 322 u8 inner_ip_ecn[0x1]; 323 u8 inner_ip_dscp[0x1]; 324 u8 inner_udp_sport[0x1]; 325 u8 inner_udp_dport[0x1]; 326 u8 inner_tcp_sport[0x1]; 327 u8 inner_tcp_dport[0x1]; 328 u8 inner_tcp_flags[0x1]; 329 u8 reserved_5[0x9]; 330 331 u8 reserved_6[0x1a]; 332 u8 bth_dst_qp[0x1]; 333 u8 reserved_7[0x4]; 334 u8 source_sqn[0x1]; 335 336 u8 reserved_8[0x20]; 337 }; 338 339 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 340 u8 ingress_general_high[0x20]; 341 342 u8 ingress_general_low[0x20]; 343 344 u8 ingress_policy_engine_high[0x20]; 345 346 u8 ingress_policy_engine_low[0x20]; 347 348 u8 ingress_vlan_membership_high[0x20]; 349 350 u8 ingress_vlan_membership_low[0x20]; 351 352 u8 ingress_tag_frame_type_high[0x20]; 353 354 u8 ingress_tag_frame_type_low[0x20]; 355 356 u8 egress_vlan_membership_high[0x20]; 357 358 u8 egress_vlan_membership_low[0x20]; 359 360 u8 loopback_filter_high[0x20]; 361 362 u8 loopback_filter_low[0x20]; 363 364 u8 egress_general_high[0x20]; 365 366 u8 egress_general_low[0x20]; 367 368 u8 reserved_at_1c0[0x40]; 369 370 u8 egress_hoq_high[0x20]; 371 372 u8 egress_hoq_low[0x20]; 373 374 u8 port_isolation_high[0x20]; 375 376 u8 port_isolation_low[0x20]; 377 378 u8 egress_policy_engine_high[0x20]; 379 380 u8 egress_policy_engine_low[0x20]; 381 382 u8 ingress_tx_link_down_high[0x20]; 383 384 u8 ingress_tx_link_down_low[0x20]; 385 386 u8 egress_stp_filter_high[0x20]; 387 388 u8 egress_stp_filter_low[0x20]; 389 390 u8 egress_hoq_stall_high[0x20]; 391 392 u8 egress_hoq_stall_low[0x20]; 393 394 u8 reserved_at_340[0x440]; 395 }; 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 flow_tag[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 encap[0x1]; 405 u8 decap[0x1]; 406 u8 reset_root_to_default[0x1]; 407 u8 reserved_at_a[0x16]; 408 409 u8 reserved_at_20[0x2]; 410 u8 log_max_ft_size[0x6]; 411 u8 reserved_at_28[0x10]; 412 u8 max_ft_level[0x8]; 413 414 u8 reserved_at_40[0x20]; 415 416 u8 reserved_at_60[0x18]; 417 u8 log_max_ft_num[0x8]; 418 419 u8 reserved_at_80[0x10]; 420 u8 log_max_flow_counter[0x8]; 421 u8 log_max_destination[0x8]; 422 423 u8 reserved_at_a0[0x18]; 424 u8 log_max_flow[0x8]; 425 426 u8 reserved_at_c0[0x40]; 427 428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 429 430 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 431 }; 432 433 struct mlx5_ifc_odp_per_transport_service_cap_bits { 434 u8 send[0x1]; 435 u8 receive[0x1]; 436 u8 write[0x1]; 437 u8 read[0x1]; 438 u8 atomic[0x1]; 439 u8 srq_receive[0x1]; 440 u8 reserved_0[0x1a]; 441 }; 442 443 struct mlx5_ifc_flow_counter_list_bits { 444 u8 reserved_0[0x10]; 445 u8 flow_counter_id[0x10]; 446 447 u8 reserved_1[0x20]; 448 }; 449 450 enum { 451 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 452 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 453 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 454 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 455 }; 456 457 struct mlx5_ifc_dest_format_struct_bits { 458 u8 destination_type[0x8]; 459 u8 destination_id[0x18]; 460 461 u8 reserved_0[0x20]; 462 }; 463 464 struct mlx5_ifc_ipv4_layout_bits { 465 u8 reserved_at_0[0x60]; 466 467 u8 ipv4[0x20]; 468 }; 469 470 struct mlx5_ifc_ipv6_layout_bits { 471 u8 ipv6[16][0x8]; 472 }; 473 474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 475 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 476 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 477 u8 reserved_at_0[0x80]; 478 }; 479 480 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 481 u8 smac_47_16[0x20]; 482 483 u8 smac_15_0[0x10]; 484 u8 ethertype[0x10]; 485 486 u8 dmac_47_16[0x20]; 487 488 u8 dmac_15_0[0x10]; 489 u8 first_prio[0x3]; 490 u8 first_cfi[0x1]; 491 u8 first_vid[0xc]; 492 493 u8 ip_protocol[0x8]; 494 u8 ip_dscp[0x6]; 495 u8 ip_ecn[0x2]; 496 u8 cvlan_tag[0x1]; 497 u8 svlan_tag[0x1]; 498 u8 frag[0x1]; 499 u8 reserved_1[0x4]; 500 u8 tcp_flags[0x9]; 501 502 u8 tcp_sport[0x10]; 503 u8 tcp_dport[0x10]; 504 505 u8 reserved_2[0x20]; 506 507 u8 udp_sport[0x10]; 508 u8 udp_dport[0x10]; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 511 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 513 }; 514 515 struct mlx5_ifc_fte_match_set_misc_bits { 516 u8 reserved_0[0x8]; 517 u8 source_sqn[0x18]; 518 519 u8 reserved_1[0x10]; 520 u8 source_port[0x10]; 521 522 u8 outer_second_prio[0x3]; 523 u8 outer_second_cfi[0x1]; 524 u8 outer_second_vid[0xc]; 525 u8 inner_second_prio[0x3]; 526 u8 inner_second_cfi[0x1]; 527 u8 inner_second_vid[0xc]; 528 529 u8 outer_second_vlan_tag[0x1]; 530 u8 inner_second_vlan_tag[0x1]; 531 u8 reserved_2[0xe]; 532 u8 gre_protocol[0x10]; 533 534 u8 gre_key_h[0x18]; 535 u8 gre_key_l[0x8]; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_3[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved4[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_5[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_6[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_7[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_8[0x8]; 555 u8 bth_dst_qp[0x18]; 556 557 u8 reserved_9[0xa0]; 558 }; 559 560 struct mlx5_ifc_cmd_pas_bits { 561 u8 pa_h[0x20]; 562 563 u8 pa_l[0x14]; 564 u8 reserved_0[0xc]; 565 }; 566 567 struct mlx5_ifc_uint64_bits { 568 u8 hi[0x20]; 569 570 u8 lo[0x20]; 571 }; 572 573 struct mlx5_ifc_application_prio_entry_bits { 574 u8 reserved_0[0x8]; 575 u8 priority[0x3]; 576 u8 reserved_1[0x2]; 577 u8 sel[0x3]; 578 u8 protocol_id[0x10]; 579 }; 580 581 struct mlx5_ifc_nodnic_ring_doorbell_bits { 582 u8 reserved_0[0x8]; 583 u8 ring_pi[0x10]; 584 u8 reserved_1[0x8]; 585 }; 586 587 enum { 588 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 589 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 590 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 591 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 592 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 593 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 594 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 595 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 596 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 597 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 598 }; 599 600 struct mlx5_ifc_ads_bits { 601 u8 fl[0x1]; 602 u8 free_ar[0x1]; 603 u8 reserved_0[0xe]; 604 u8 pkey_index[0x10]; 605 606 u8 reserved_1[0x8]; 607 u8 grh[0x1]; 608 u8 mlid[0x7]; 609 u8 rlid[0x10]; 610 611 u8 ack_timeout[0x5]; 612 u8 reserved_2[0x3]; 613 u8 src_addr_index[0x8]; 614 u8 log_rtm[0x4]; 615 u8 stat_rate[0x4]; 616 u8 hop_limit[0x8]; 617 618 u8 reserved_3[0x4]; 619 u8 tclass[0x8]; 620 u8 flow_label[0x14]; 621 622 u8 rgid_rip[16][0x8]; 623 624 u8 reserved_4[0x4]; 625 u8 f_dscp[0x1]; 626 u8 f_ecn[0x1]; 627 u8 reserved_5[0x1]; 628 u8 f_eth_prio[0x1]; 629 u8 ecn[0x2]; 630 u8 dscp[0x6]; 631 u8 udp_sport[0x10]; 632 633 u8 dei_cfi[0x1]; 634 u8 eth_prio[0x3]; 635 u8 sl[0x4]; 636 u8 port[0x8]; 637 u8 rmac_47_32[0x10]; 638 639 u8 rmac_31_0[0x20]; 640 }; 641 642 struct mlx5_ifc_diagnostic_counter_cap_bits { 643 u8 sync[0x1]; 644 u8 reserved_0[0xf]; 645 u8 counter_id[0x10]; 646 }; 647 648 struct mlx5_ifc_debug_cap_bits { 649 u8 reserved_0[0x18]; 650 u8 log_max_samples[0x8]; 651 652 u8 single[0x1]; 653 u8 repetitive[0x1]; 654 u8 health_mon_rx_activity[0x1]; 655 u8 reserved_1[0x15]; 656 u8 log_min_sample_period[0x8]; 657 658 u8 reserved_2[0x1c0]; 659 660 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 661 }; 662 663 struct mlx5_ifc_qos_cap_bits { 664 u8 packet_pacing[0x1]; 665 u8 esw_scheduling[0x1]; 666 u8 esw_bw_share[0x1]; 667 u8 esw_rate_limit[0x1]; 668 u8 hll[0x1]; 669 u8 packet_pacing_burst_bound[0x1]; 670 u8 packet_pacing_typical_size[0x1]; 671 u8 reserved_at_7[0x19]; 672 673 u8 reserved_at_20[0x20]; 674 675 u8 packet_pacing_max_rate[0x20]; 676 677 u8 packet_pacing_min_rate[0x20]; 678 679 u8 reserved_at_80[0x10]; 680 u8 packet_pacing_rate_table_size[0x10]; 681 682 u8 esw_element_type[0x10]; 683 u8 esw_tsar_type[0x10]; 684 685 u8 reserved_at_c0[0x10]; 686 u8 max_qos_para_vport[0x10]; 687 688 u8 max_tsar_bw_share[0x20]; 689 690 u8 reserved_at_100[0x700]; 691 }; 692 693 struct mlx5_ifc_snapshot_cap_bits { 694 u8 reserved_0[0x1d]; 695 u8 suspend_qp_uc[0x1]; 696 u8 suspend_qp_ud[0x1]; 697 u8 suspend_qp_rc[0x1]; 698 699 u8 reserved_1[0x1c]; 700 u8 restore_pd[0x1]; 701 u8 restore_uar[0x1]; 702 u8 restore_mkey[0x1]; 703 u8 restore_qp[0x1]; 704 705 u8 reserved_2[0x1e]; 706 u8 named_mkey[0x1]; 707 u8 named_qp[0x1]; 708 709 u8 reserved_3[0x7a0]; 710 }; 711 712 struct mlx5_ifc_e_switch_cap_bits { 713 u8 vport_svlan_strip[0x1]; 714 u8 vport_cvlan_strip[0x1]; 715 u8 vport_svlan_insert[0x1]; 716 u8 vport_cvlan_insert_if_not_exist[0x1]; 717 u8 vport_cvlan_insert_overwrite[0x1]; 718 719 u8 reserved_0[0x19]; 720 721 u8 nic_vport_node_guid_modify[0x1]; 722 u8 nic_vport_port_guid_modify[0x1]; 723 724 u8 reserved_1[0x7e0]; 725 }; 726 727 struct mlx5_ifc_flow_table_eswitch_cap_bits { 728 u8 reserved_0[0x200]; 729 730 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 731 732 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 733 734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 735 736 u8 reserved_1[0x7800]; 737 }; 738 739 struct mlx5_ifc_flow_table_nic_cap_bits { 740 u8 nic_rx_multi_path_tirs[0x1]; 741 u8 nic_rx_multi_path_tirs_fts[0x1]; 742 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 743 u8 reserved_at_3[0x1fd]; 744 745 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 756 757 u8 reserved_1[0x7200]; 758 }; 759 760 struct mlx5_ifc_pddr_module_info_bits { 761 u8 cable_technology[0x8]; 762 u8 cable_breakout[0x8]; 763 u8 ext_ethernet_compliance_code[0x8]; 764 u8 ethernet_compliance_code[0x8]; 765 766 u8 cable_type[0x4]; 767 u8 cable_vendor[0x4]; 768 u8 cable_length[0x8]; 769 u8 cable_identifier[0x8]; 770 u8 cable_power_class[0x8]; 771 772 u8 reserved_at_40[0x8]; 773 u8 cable_rx_amp[0x8]; 774 u8 cable_rx_emphasis[0x8]; 775 u8 cable_tx_equalization[0x8]; 776 777 u8 reserved_at_60[0x8]; 778 u8 cable_attenuation_12g[0x8]; 779 u8 cable_attenuation_7g[0x8]; 780 u8 cable_attenuation_5g[0x8]; 781 782 u8 reserved_at_80[0x8]; 783 u8 rx_cdr_cap[0x4]; 784 u8 tx_cdr_cap[0x4]; 785 u8 reserved_at_90[0x4]; 786 u8 rx_cdr_state[0x4]; 787 u8 reserved_at_98[0x4]; 788 u8 tx_cdr_state[0x4]; 789 790 u8 vendor_name[16][0x8]; 791 792 u8 vendor_pn[16][0x8]; 793 794 u8 vendor_rev[0x20]; 795 796 u8 fw_version[0x20]; 797 798 u8 vendor_sn[16][0x8]; 799 800 u8 temperature[0x10]; 801 u8 voltage[0x10]; 802 803 u8 rx_power_lane0[0x10]; 804 u8 rx_power_lane1[0x10]; 805 806 u8 rx_power_lane2[0x10]; 807 u8 rx_power_lane3[0x10]; 808 809 u8 reserved_at_2c0[0x40]; 810 811 u8 tx_power_lane0[0x10]; 812 u8 tx_power_lane1[0x10]; 813 814 u8 tx_power_lane2[0x10]; 815 u8 tx_power_lane3[0x10]; 816 817 u8 reserved_at_340[0x40]; 818 819 u8 tx_bias_lane0[0x10]; 820 u8 tx_bias_lane1[0x10]; 821 822 u8 tx_bias_lane2[0x10]; 823 u8 tx_bias_lane3[0x10]; 824 825 u8 reserved_at_3c0[0x40]; 826 827 u8 temperature_high_th[0x10]; 828 u8 temperature_low_th[0x10]; 829 830 u8 voltage_high_th[0x10]; 831 u8 voltage_low_th[0x10]; 832 833 u8 rx_power_high_th[0x10]; 834 u8 rx_power_low_th[0x10]; 835 836 u8 tx_power_high_th[0x10]; 837 u8 tx_power_low_th[0x10]; 838 839 u8 tx_bias_high_th[0x10]; 840 u8 tx_bias_low_th[0x10]; 841 842 u8 reserved_at_4a0[0x10]; 843 u8 wavelength[0x10]; 844 845 u8 reserved_at_4c0[0x300]; 846 }; 847 848 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 849 u8 csum_cap[0x1]; 850 u8 vlan_cap[0x1]; 851 u8 lro_cap[0x1]; 852 u8 lro_psh_flag[0x1]; 853 u8 lro_time_stamp[0x1]; 854 u8 lro_max_msg_sz_mode[0x2]; 855 u8 wqe_vlan_insert[0x1]; 856 u8 self_lb_en_modifiable[0x1]; 857 u8 self_lb_mc[0x1]; 858 u8 self_lb_uc[0x1]; 859 u8 max_lso_cap[0x5]; 860 u8 multi_pkt_send_wqe[0x2]; 861 u8 wqe_inline_mode[0x2]; 862 u8 rss_ind_tbl_cap[0x4]; 863 u8 scatter_fcs[0x1]; 864 u8 reserved_1[0x2]; 865 u8 tunnel_lso_const_out_ip_id[0x1]; 866 u8 tunnel_lro_gre[0x1]; 867 u8 tunnel_lro_vxlan[0x1]; 868 u8 tunnel_statless_gre[0x1]; 869 u8 tunnel_stateless_vxlan[0x1]; 870 871 u8 swp[0x1]; 872 u8 swp_csum[0x1]; 873 u8 swp_lso[0x1]; 874 u8 reserved_2[0x1b]; 875 u8 max_geneve_opt_len[0x1]; 876 u8 tunnel_stateless_geneve_rx[0x1]; 877 878 u8 reserved_3[0x10]; 879 u8 lro_min_mss_size[0x10]; 880 881 u8 reserved_4[0x120]; 882 883 u8 lro_timer_supported_periods[4][0x20]; 884 885 u8 reserved_5[0x600]; 886 }; 887 888 enum { 889 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 890 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 891 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 892 }; 893 894 struct mlx5_ifc_roce_cap_bits { 895 u8 roce_apm[0x1]; 896 u8 rts2rts_primary_eth_prio[0x1]; 897 u8 roce_rx_allow_untagged[0x1]; 898 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 899 900 u8 reserved_0[0x1c]; 901 902 u8 reserved_1[0x60]; 903 904 u8 reserved_2[0xc]; 905 u8 l3_type[0x4]; 906 u8 reserved_3[0x8]; 907 u8 roce_version[0x8]; 908 909 u8 reserved_4[0x10]; 910 u8 r_roce_dest_udp_port[0x10]; 911 912 u8 r_roce_max_src_udp_port[0x10]; 913 u8 r_roce_min_src_udp_port[0x10]; 914 915 u8 reserved_5[0x10]; 916 u8 roce_address_table_size[0x10]; 917 918 u8 reserved_6[0x700]; 919 }; 920 921 enum { 922 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 923 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 924 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 925 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 926 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 927 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 928 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 929 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 930 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 931 }; 932 933 enum { 934 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 935 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 936 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 937 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 938 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 939 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 940 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 941 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 942 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 943 }; 944 945 struct mlx5_ifc_atomic_caps_bits { 946 u8 reserved_0[0x40]; 947 948 u8 atomic_req_8B_endianess_mode[0x2]; 949 u8 reserved_1[0x4]; 950 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 951 952 u8 reserved_2[0x19]; 953 954 u8 reserved_3[0x20]; 955 956 u8 reserved_4[0x10]; 957 u8 atomic_operations[0x10]; 958 959 u8 reserved_5[0x10]; 960 u8 atomic_size_qp[0x10]; 961 962 u8 reserved_6[0x10]; 963 u8 atomic_size_dc[0x10]; 964 965 u8 reserved_7[0x720]; 966 }; 967 968 struct mlx5_ifc_odp_cap_bits { 969 u8 reserved_0[0x40]; 970 971 u8 sig[0x1]; 972 u8 reserved_1[0x1f]; 973 974 u8 reserved_2[0x20]; 975 976 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 977 978 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 979 980 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 981 982 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 983 984 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 985 986 u8 reserved_3[0x6e0]; 987 }; 988 989 enum { 990 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 991 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 992 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 993 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 994 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 995 }; 996 997 enum { 998 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 999 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1000 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1001 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1002 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1003 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1004 }; 1005 1006 enum { 1007 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1008 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1009 }; 1010 1011 enum { 1012 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1013 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1014 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1015 }; 1016 1017 struct mlx5_ifc_cmd_hca_cap_bits { 1018 u8 reserved_0[0x80]; 1019 1020 u8 log_max_srq_sz[0x8]; 1021 u8 log_max_qp_sz[0x8]; 1022 u8 reserved_1[0xb]; 1023 u8 log_max_qp[0x5]; 1024 1025 u8 reserved_2[0xb]; 1026 u8 log_max_srq[0x5]; 1027 u8 reserved_3[0x10]; 1028 1029 u8 reserved_4[0x8]; 1030 u8 log_max_cq_sz[0x8]; 1031 u8 reserved_5[0xb]; 1032 u8 log_max_cq[0x5]; 1033 1034 u8 log_max_eq_sz[0x8]; 1035 u8 relaxed_ordering_write[1]; 1036 u8 reserved_6[0x1]; 1037 u8 log_max_mkey[0x6]; 1038 u8 reserved_7[0xb]; 1039 u8 fast_teardown[0x1]; 1040 u8 log_max_eq[0x4]; 1041 1042 u8 max_indirection[0x8]; 1043 u8 reserved_8[0x1]; 1044 u8 log_max_mrw_sz[0x7]; 1045 u8 force_teardown[0x1]; 1046 u8 reserved_9[0x1]; 1047 u8 log_max_bsf_list_size[0x6]; 1048 u8 reserved_10[0x2]; 1049 u8 log_max_klm_list_size[0x6]; 1050 1051 u8 reserved_11[0xa]; 1052 u8 log_max_ra_req_dc[0x6]; 1053 u8 reserved_12[0xa]; 1054 u8 log_max_ra_res_dc[0x6]; 1055 1056 u8 reserved_13[0xa]; 1057 u8 log_max_ra_req_qp[0x6]; 1058 u8 reserved_14[0xa]; 1059 u8 log_max_ra_res_qp[0x6]; 1060 1061 u8 pad_cap[0x1]; 1062 u8 cc_query_allowed[0x1]; 1063 u8 cc_modify_allowed[0x1]; 1064 u8 start_pad[0x1]; 1065 u8 cache_line_128byte[0x1]; 1066 u8 reserved_at_165[0xa]; 1067 u8 qcam_reg[0x1]; 1068 u8 gid_table_size[0x10]; 1069 1070 u8 out_of_seq_cnt[0x1]; 1071 u8 vport_counters[0x1]; 1072 u8 retransmission_q_counters[0x1]; 1073 u8 debug[0x1]; 1074 u8 modify_rq_counters_set_id[0x1]; 1075 u8 rq_delay_drop[0x1]; 1076 u8 max_qp_cnt[0xa]; 1077 u8 pkey_table_size[0x10]; 1078 1079 u8 vport_group_manager[0x1]; 1080 u8 vhca_group_manager[0x1]; 1081 u8 ib_virt[0x1]; 1082 u8 eth_virt[0x1]; 1083 u8 reserved_17[0x1]; 1084 u8 ets[0x1]; 1085 u8 nic_flow_table[0x1]; 1086 u8 eswitch_flow_table[0x1]; 1087 u8 reserved_18[0x1]; 1088 u8 mcam_reg[0x1]; 1089 u8 pcam_reg[0x1]; 1090 u8 local_ca_ack_delay[0x5]; 1091 u8 port_module_event[0x1]; 1092 u8 reserved_19[0x5]; 1093 u8 port_type[0x2]; 1094 u8 num_ports[0x8]; 1095 1096 u8 snapshot[0x1]; 1097 u8 reserved_20[0x2]; 1098 u8 log_max_msg[0x5]; 1099 u8 reserved_21[0x4]; 1100 u8 max_tc[0x4]; 1101 u8 temp_warn_event[0x1]; 1102 u8 dcbx[0x1]; 1103 u8 general_notification_event[0x1]; 1104 u8 reserved_at_1d3[0x2]; 1105 u8 fpga[0x1]; 1106 u8 rol_s[0x1]; 1107 u8 rol_g[0x1]; 1108 u8 reserved_23[0x1]; 1109 u8 wol_s[0x1]; 1110 u8 wol_g[0x1]; 1111 u8 wol_a[0x1]; 1112 u8 wol_b[0x1]; 1113 u8 wol_m[0x1]; 1114 u8 wol_u[0x1]; 1115 u8 wol_p[0x1]; 1116 1117 u8 stat_rate_support[0x10]; 1118 u8 reserved_24[0xc]; 1119 u8 cqe_version[0x4]; 1120 1121 u8 compact_address_vector[0x1]; 1122 u8 striding_rq[0x1]; 1123 u8 reserved_25[0x1]; 1124 u8 ipoib_enhanced_offloads[0x1]; 1125 u8 ipoib_ipoib_offloads[0x1]; 1126 u8 reserved_26[0x8]; 1127 u8 dc_connect_qp[0x1]; 1128 u8 dc_cnak_trace[0x1]; 1129 u8 drain_sigerr[0x1]; 1130 u8 cmdif_checksum[0x2]; 1131 u8 sigerr_cqe[0x1]; 1132 u8 reserved_27[0x1]; 1133 u8 wq_signature[0x1]; 1134 u8 sctr_data_cqe[0x1]; 1135 u8 reserved_28[0x1]; 1136 u8 sho[0x1]; 1137 u8 tph[0x1]; 1138 u8 rf[0x1]; 1139 u8 dct[0x1]; 1140 u8 qos[0x1]; 1141 u8 eth_net_offloads[0x1]; 1142 u8 roce[0x1]; 1143 u8 atomic[0x1]; 1144 u8 reserved_30[0x1]; 1145 1146 u8 cq_oi[0x1]; 1147 u8 cq_resize[0x1]; 1148 u8 cq_moderation[0x1]; 1149 u8 cq_period_mode_modify[0x1]; 1150 u8 cq_invalidate[0x1]; 1151 u8 reserved_at_225[0x1]; 1152 u8 cq_eq_remap[0x1]; 1153 u8 pg[0x1]; 1154 u8 block_lb_mc[0x1]; 1155 u8 exponential_backoff[0x1]; 1156 u8 scqe_break_moderation[0x1]; 1157 u8 cq_period_start_from_cqe[0x1]; 1158 u8 cd[0x1]; 1159 u8 atm[0x1]; 1160 u8 apm[0x1]; 1161 u8 imaicl[0x1]; 1162 u8 reserved_32[0x6]; 1163 u8 qkv[0x1]; 1164 u8 pkv[0x1]; 1165 u8 set_deth_sqpn[0x1]; 1166 u8 reserved_33[0x3]; 1167 u8 xrc[0x1]; 1168 u8 ud[0x1]; 1169 u8 uc[0x1]; 1170 u8 rc[0x1]; 1171 1172 u8 reserved_34[0xa]; 1173 u8 uar_sz[0x6]; 1174 u8 reserved_35[0x8]; 1175 u8 log_pg_sz[0x8]; 1176 1177 u8 bf[0x1]; 1178 u8 driver_version[0x1]; 1179 u8 pad_tx_eth_packet[0x1]; 1180 u8 reserved_36[0x8]; 1181 u8 log_bf_reg_size[0x5]; 1182 u8 reserved_37[0x10]; 1183 1184 u8 num_of_diagnostic_counters[0x10]; 1185 u8 max_wqe_sz_sq[0x10]; 1186 1187 u8 reserved_38[0x10]; 1188 u8 max_wqe_sz_rq[0x10]; 1189 1190 u8 reserved_39[0x10]; 1191 u8 max_wqe_sz_sq_dc[0x10]; 1192 1193 u8 reserved_40[0x7]; 1194 u8 max_qp_mcg[0x19]; 1195 1196 u8 reserved_41[0x18]; 1197 u8 log_max_mcg[0x8]; 1198 1199 u8 reserved_42[0x3]; 1200 u8 log_max_transport_domain[0x5]; 1201 u8 reserved_43[0x3]; 1202 u8 log_max_pd[0x5]; 1203 u8 reserved_44[0xb]; 1204 u8 log_max_xrcd[0x5]; 1205 1206 u8 nic_receive_steering_discard[0x1]; 1207 u8 reserved_45[0x7]; 1208 u8 log_max_flow_counter_bulk[0x8]; 1209 u8 max_flow_counter[0x10]; 1210 1211 u8 reserved_46[0x3]; 1212 u8 log_max_rq[0x5]; 1213 u8 reserved_47[0x3]; 1214 u8 log_max_sq[0x5]; 1215 u8 reserved_48[0x3]; 1216 u8 log_max_tir[0x5]; 1217 u8 reserved_49[0x3]; 1218 u8 log_max_tis[0x5]; 1219 1220 u8 basic_cyclic_rcv_wqe[0x1]; 1221 u8 reserved_50[0x2]; 1222 u8 log_max_rmp[0x5]; 1223 u8 reserved_51[0x3]; 1224 u8 log_max_rqt[0x5]; 1225 u8 reserved_52[0x3]; 1226 u8 log_max_rqt_size[0x5]; 1227 u8 reserved_53[0x3]; 1228 u8 log_max_tis_per_sq[0x5]; 1229 1230 u8 reserved_54[0x3]; 1231 u8 log_max_stride_sz_rq[0x5]; 1232 u8 reserved_55[0x3]; 1233 u8 log_min_stride_sz_rq[0x5]; 1234 u8 reserved_56[0x3]; 1235 u8 log_max_stride_sz_sq[0x5]; 1236 u8 reserved_57[0x3]; 1237 u8 log_min_stride_sz_sq[0x5]; 1238 1239 u8 reserved_58[0x1b]; 1240 u8 log_max_wq_sz[0x5]; 1241 1242 u8 nic_vport_change_event[0x1]; 1243 u8 disable_local_lb[0x1]; 1244 u8 reserved_59[0x9]; 1245 u8 log_max_vlan_list[0x5]; 1246 u8 reserved_60[0x3]; 1247 u8 log_max_current_mc_list[0x5]; 1248 u8 reserved_61[0x3]; 1249 u8 log_max_current_uc_list[0x5]; 1250 1251 u8 reserved_62[0x80]; 1252 1253 u8 reserved_63[0x3]; 1254 u8 log_max_l2_table[0x5]; 1255 u8 reserved_64[0x8]; 1256 u8 log_uar_page_sz[0x10]; 1257 1258 u8 reserved_65[0x20]; 1259 1260 u8 device_frequency_mhz[0x20]; 1261 1262 u8 device_frequency_khz[0x20]; 1263 1264 u8 reserved_66[0x80]; 1265 1266 u8 log_max_atomic_size_qp[0x8]; 1267 u8 reserved_67[0x10]; 1268 u8 log_max_atomic_size_dc[0x8]; 1269 1270 u8 reserved_68[0x1f]; 1271 u8 cqe_compression[0x1]; 1272 1273 u8 cqe_compression_timeout[0x10]; 1274 u8 cqe_compression_max_num[0x10]; 1275 1276 u8 reserved_69[0x220]; 1277 }; 1278 1279 enum mlx5_flow_destination_type { 1280 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1281 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1282 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1283 }; 1284 1285 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1286 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1287 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1288 u8 reserved_0[0x40]; 1289 }; 1290 1291 struct mlx5_ifc_fte_match_param_bits { 1292 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1293 1294 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1295 1296 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1297 1298 u8 reserved_0[0xa00]; 1299 }; 1300 1301 enum { 1302 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1303 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1304 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1305 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1306 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1307 }; 1308 1309 struct mlx5_ifc_rx_hash_field_select_bits { 1310 u8 l3_prot_type[0x1]; 1311 u8 l4_prot_type[0x1]; 1312 u8 selected_fields[0x1e]; 1313 }; 1314 1315 enum { 1316 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1317 MLX5_WQ_TYPE_CYCLIC = 0x1, 1318 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1319 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1320 }; 1321 1322 enum rq_type { 1323 RQ_TYPE_NONE, 1324 RQ_TYPE_STRIDE, 1325 }; 1326 1327 enum { 1328 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1329 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1330 }; 1331 1332 struct mlx5_ifc_wq_bits { 1333 u8 wq_type[0x4]; 1334 u8 wq_signature[0x1]; 1335 u8 end_padding_mode[0x2]; 1336 u8 cd_slave[0x1]; 1337 u8 reserved_0[0x18]; 1338 1339 u8 hds_skip_first_sge[0x1]; 1340 u8 log2_hds_buf_size[0x3]; 1341 u8 reserved_1[0x7]; 1342 u8 page_offset[0x5]; 1343 u8 lwm[0x10]; 1344 1345 u8 reserved_2[0x8]; 1346 u8 pd[0x18]; 1347 1348 u8 reserved_3[0x8]; 1349 u8 uar_page[0x18]; 1350 1351 u8 dbr_addr[0x40]; 1352 1353 u8 hw_counter[0x20]; 1354 1355 u8 sw_counter[0x20]; 1356 1357 u8 reserved_4[0xc]; 1358 u8 log_wq_stride[0x4]; 1359 u8 reserved_5[0x3]; 1360 u8 log_wq_pg_sz[0x5]; 1361 u8 reserved_6[0x3]; 1362 u8 log_wq_sz[0x5]; 1363 1364 u8 reserved_7[0x15]; 1365 u8 single_wqe_log_num_of_strides[0x3]; 1366 u8 two_byte_shift_en[0x1]; 1367 u8 reserved_8[0x4]; 1368 u8 single_stride_log_num_of_bytes[0x3]; 1369 1370 u8 reserved_9[0x4c0]; 1371 1372 struct mlx5_ifc_cmd_pas_bits pas[0]; 1373 }; 1374 1375 struct mlx5_ifc_rq_num_bits { 1376 u8 reserved_0[0x8]; 1377 u8 rq_num[0x18]; 1378 }; 1379 1380 struct mlx5_ifc_mac_address_layout_bits { 1381 u8 reserved_0[0x10]; 1382 u8 mac_addr_47_32[0x10]; 1383 1384 u8 mac_addr_31_0[0x20]; 1385 }; 1386 1387 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1388 u8 reserved_0[0xa0]; 1389 1390 u8 min_time_between_cnps[0x20]; 1391 1392 u8 reserved_1[0x12]; 1393 u8 cnp_dscp[0x6]; 1394 u8 reserved_2[0x4]; 1395 u8 cnp_prio_mode[0x1]; 1396 u8 cnp_802p_prio[0x3]; 1397 1398 u8 reserved_3[0x720]; 1399 }; 1400 1401 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1402 u8 reserved_0[0x60]; 1403 1404 u8 reserved_1[0x4]; 1405 u8 clamp_tgt_rate[0x1]; 1406 u8 reserved_2[0x3]; 1407 u8 clamp_tgt_rate_after_time_inc[0x1]; 1408 u8 reserved_3[0x17]; 1409 1410 u8 reserved_4[0x20]; 1411 1412 u8 rpg_time_reset[0x20]; 1413 1414 u8 rpg_byte_reset[0x20]; 1415 1416 u8 rpg_threshold[0x20]; 1417 1418 u8 rpg_max_rate[0x20]; 1419 1420 u8 rpg_ai_rate[0x20]; 1421 1422 u8 rpg_hai_rate[0x20]; 1423 1424 u8 rpg_gd[0x20]; 1425 1426 u8 rpg_min_dec_fac[0x20]; 1427 1428 u8 rpg_min_rate[0x20]; 1429 1430 u8 reserved_5[0xe0]; 1431 1432 u8 rate_to_set_on_first_cnp[0x20]; 1433 1434 u8 dce_tcp_g[0x20]; 1435 1436 u8 dce_tcp_rtt[0x20]; 1437 1438 u8 rate_reduce_monitor_period[0x20]; 1439 1440 u8 reserved_6[0x20]; 1441 1442 u8 initial_alpha_value[0x20]; 1443 1444 u8 reserved_7[0x4a0]; 1445 }; 1446 1447 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1448 u8 reserved_0[0x80]; 1449 1450 u8 rppp_max_rps[0x20]; 1451 1452 u8 rpg_time_reset[0x20]; 1453 1454 u8 rpg_byte_reset[0x20]; 1455 1456 u8 rpg_threshold[0x20]; 1457 1458 u8 rpg_max_rate[0x20]; 1459 1460 u8 rpg_ai_rate[0x20]; 1461 1462 u8 rpg_hai_rate[0x20]; 1463 1464 u8 rpg_gd[0x20]; 1465 1466 u8 rpg_min_dec_fac[0x20]; 1467 1468 u8 rpg_min_rate[0x20]; 1469 1470 u8 reserved_1[0x640]; 1471 }; 1472 1473 enum { 1474 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1475 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1476 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1477 }; 1478 1479 struct mlx5_ifc_resize_field_select_bits { 1480 u8 resize_field_select[0x20]; 1481 }; 1482 1483 enum { 1484 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1485 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1486 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1487 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1488 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1489 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1490 }; 1491 1492 struct mlx5_ifc_modify_field_select_bits { 1493 u8 modify_field_select[0x20]; 1494 }; 1495 1496 struct mlx5_ifc_field_select_r_roce_np_bits { 1497 u8 field_select_r_roce_np[0x20]; 1498 }; 1499 1500 enum { 1501 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1502 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1503 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1504 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1505 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1506 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1507 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1508 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1509 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1510 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1511 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1512 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1513 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1514 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1515 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1516 }; 1517 1518 struct mlx5_ifc_field_select_r_roce_rp_bits { 1519 u8 field_select_r_roce_rp[0x20]; 1520 }; 1521 1522 enum { 1523 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1524 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1525 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1526 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1527 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1528 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1529 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1530 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1531 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1532 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1533 }; 1534 1535 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1536 u8 field_select_8021qaurp[0x20]; 1537 }; 1538 1539 struct mlx5_ifc_pptb_reg_bits { 1540 u8 reserved_at_0[0x2]; 1541 u8 mm[0x2]; 1542 u8 reserved_at_4[0x4]; 1543 u8 local_port[0x8]; 1544 u8 reserved_at_10[0x6]; 1545 u8 cm[0x1]; 1546 u8 um[0x1]; 1547 u8 pm[0x8]; 1548 1549 u8 prio_x_buff[0x20]; 1550 1551 u8 pm_msb[0x8]; 1552 u8 reserved_at_48[0x10]; 1553 u8 ctrl_buff[0x4]; 1554 u8 untagged_buff[0x4]; 1555 }; 1556 1557 struct mlx5_ifc_dcbx_app_reg_bits { 1558 u8 reserved_0[0x8]; 1559 u8 port_number[0x8]; 1560 u8 reserved_1[0x10]; 1561 1562 u8 reserved_2[0x1a]; 1563 u8 num_app_prio[0x6]; 1564 1565 u8 reserved_3[0x40]; 1566 1567 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1568 }; 1569 1570 struct mlx5_ifc_dcbx_param_reg_bits { 1571 u8 dcbx_cee_cap[0x1]; 1572 u8 dcbx_ieee_cap[0x1]; 1573 u8 dcbx_standby_cap[0x1]; 1574 u8 reserved_0[0x5]; 1575 u8 port_number[0x8]; 1576 u8 reserved_1[0xa]; 1577 u8 max_application_table_size[0x6]; 1578 1579 u8 reserved_2[0x15]; 1580 u8 version_oper[0x3]; 1581 u8 reserved_3[0x5]; 1582 u8 version_admin[0x3]; 1583 1584 u8 willing_admin[0x1]; 1585 u8 reserved_4[0x3]; 1586 u8 pfc_cap_oper[0x4]; 1587 u8 reserved_5[0x4]; 1588 u8 pfc_cap_admin[0x4]; 1589 u8 reserved_6[0x4]; 1590 u8 num_of_tc_oper[0x4]; 1591 u8 reserved_7[0x4]; 1592 u8 num_of_tc_admin[0x4]; 1593 1594 u8 remote_willing[0x1]; 1595 u8 reserved_8[0x3]; 1596 u8 remote_pfc_cap[0x4]; 1597 u8 reserved_9[0x14]; 1598 u8 remote_num_of_tc[0x4]; 1599 1600 u8 reserved_10[0x18]; 1601 u8 error[0x8]; 1602 1603 u8 reserved_11[0x160]; 1604 }; 1605 1606 struct mlx5_ifc_qhll_bits { 1607 u8 reserved_at_0[0x8]; 1608 u8 local_port[0x8]; 1609 u8 reserved_at_10[0x10]; 1610 1611 u8 reserved_at_20[0x1b]; 1612 u8 hll_time[0x5]; 1613 1614 u8 stall_en[0x1]; 1615 u8 reserved_at_41[0x1c]; 1616 u8 stall_cnt[0x3]; 1617 }; 1618 1619 struct mlx5_ifc_qetcr_reg_bits { 1620 u8 operation_type[0x2]; 1621 u8 cap_local_admin[0x1]; 1622 u8 cap_remote_admin[0x1]; 1623 u8 reserved_0[0x4]; 1624 u8 port_number[0x8]; 1625 u8 reserved_1[0x10]; 1626 1627 u8 reserved_2[0x20]; 1628 1629 u8 tc[8][0x40]; 1630 1631 u8 global_configuration[0x40]; 1632 }; 1633 1634 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1635 u8 queue_address_63_32[0x20]; 1636 1637 u8 queue_address_31_12[0x14]; 1638 u8 reserved_0[0x6]; 1639 u8 log_size[0x6]; 1640 1641 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1642 1643 u8 reserved_1[0x8]; 1644 u8 queue_number[0x18]; 1645 1646 u8 q_key[0x20]; 1647 1648 u8 reserved_2[0x10]; 1649 u8 pkey_index[0x10]; 1650 1651 u8 reserved_3[0x40]; 1652 }; 1653 1654 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1655 u8 reserved_0[0x8]; 1656 u8 cq_ci[0x10]; 1657 u8 reserved_1[0x8]; 1658 }; 1659 1660 enum { 1661 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1662 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1663 }; 1664 1665 enum { 1666 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1667 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1668 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1669 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1670 }; 1671 1672 struct mlx5_ifc_nodnic_event_word_bits { 1673 u8 driver_reset_needed[0x1]; 1674 u8 port_management_change_event[0x1]; 1675 u8 reserved_0[0x19]; 1676 u8 link_type[0x1]; 1677 u8 port_state[0x4]; 1678 }; 1679 1680 struct mlx5_ifc_nic_vport_change_event_bits { 1681 u8 reserved_0[0x10]; 1682 u8 vport_num[0x10]; 1683 1684 u8 reserved_1[0xc0]; 1685 }; 1686 1687 struct mlx5_ifc_pages_req_event_bits { 1688 u8 reserved_0[0x10]; 1689 u8 function_id[0x10]; 1690 1691 u8 num_pages[0x20]; 1692 1693 u8 reserved_1[0xa0]; 1694 }; 1695 1696 struct mlx5_ifc_cmd_inter_comp_event_bits { 1697 u8 command_completion_vector[0x20]; 1698 1699 u8 reserved_0[0xc0]; 1700 }; 1701 1702 struct mlx5_ifc_stall_vl_event_bits { 1703 u8 reserved_0[0x18]; 1704 u8 port_num[0x1]; 1705 u8 reserved_1[0x3]; 1706 u8 vl[0x4]; 1707 1708 u8 reserved_2[0xa0]; 1709 }; 1710 1711 struct mlx5_ifc_db_bf_congestion_event_bits { 1712 u8 event_subtype[0x8]; 1713 u8 reserved_0[0x8]; 1714 u8 congestion_level[0x8]; 1715 u8 reserved_1[0x8]; 1716 1717 u8 reserved_2[0xa0]; 1718 }; 1719 1720 struct mlx5_ifc_gpio_event_bits { 1721 u8 reserved_0[0x60]; 1722 1723 u8 gpio_event_hi[0x20]; 1724 1725 u8 gpio_event_lo[0x20]; 1726 1727 u8 reserved_1[0x40]; 1728 }; 1729 1730 struct mlx5_ifc_port_state_change_event_bits { 1731 u8 reserved_0[0x40]; 1732 1733 u8 port_num[0x4]; 1734 u8 reserved_1[0x1c]; 1735 1736 u8 reserved_2[0x80]; 1737 }; 1738 1739 struct mlx5_ifc_dropped_packet_logged_bits { 1740 u8 reserved_0[0xe0]; 1741 }; 1742 1743 enum { 1744 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1745 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1746 }; 1747 1748 struct mlx5_ifc_cq_error_bits { 1749 u8 reserved_0[0x8]; 1750 u8 cqn[0x18]; 1751 1752 u8 reserved_1[0x20]; 1753 1754 u8 reserved_2[0x18]; 1755 u8 syndrome[0x8]; 1756 1757 u8 reserved_3[0x80]; 1758 }; 1759 1760 struct mlx5_ifc_rdma_page_fault_event_bits { 1761 u8 bytes_commited[0x20]; 1762 1763 u8 r_key[0x20]; 1764 1765 u8 reserved_0[0x10]; 1766 u8 packet_len[0x10]; 1767 1768 u8 rdma_op_len[0x20]; 1769 1770 u8 rdma_va[0x40]; 1771 1772 u8 reserved_1[0x5]; 1773 u8 rdma[0x1]; 1774 u8 write[0x1]; 1775 u8 requestor[0x1]; 1776 u8 qp_number[0x18]; 1777 }; 1778 1779 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1780 u8 bytes_committed[0x20]; 1781 1782 u8 reserved_0[0x10]; 1783 u8 wqe_index[0x10]; 1784 1785 u8 reserved_1[0x10]; 1786 u8 len[0x10]; 1787 1788 u8 reserved_2[0x60]; 1789 1790 u8 reserved_3[0x5]; 1791 u8 rdma[0x1]; 1792 u8 write_read[0x1]; 1793 u8 requestor[0x1]; 1794 u8 qpn[0x18]; 1795 }; 1796 1797 enum { 1798 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1799 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1800 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1801 }; 1802 1803 struct mlx5_ifc_qp_events_bits { 1804 u8 reserved_0[0xa0]; 1805 1806 u8 type[0x8]; 1807 u8 reserved_1[0x18]; 1808 1809 u8 reserved_2[0x8]; 1810 u8 qpn_rqn_sqn[0x18]; 1811 }; 1812 1813 struct mlx5_ifc_dct_events_bits { 1814 u8 reserved_0[0xc0]; 1815 1816 u8 reserved_1[0x8]; 1817 u8 dct_number[0x18]; 1818 }; 1819 1820 struct mlx5_ifc_comp_event_bits { 1821 u8 reserved_0[0xc0]; 1822 1823 u8 reserved_1[0x8]; 1824 u8 cq_number[0x18]; 1825 }; 1826 1827 struct mlx5_ifc_fw_version_bits { 1828 u8 major[0x10]; 1829 u8 reserved_0[0x10]; 1830 1831 u8 minor[0x10]; 1832 u8 subminor[0x10]; 1833 1834 u8 second[0x8]; 1835 u8 minute[0x8]; 1836 u8 hour[0x8]; 1837 u8 reserved_1[0x8]; 1838 1839 u8 year[0x10]; 1840 u8 month[0x8]; 1841 u8 day[0x8]; 1842 }; 1843 1844 enum { 1845 MLX5_QPC_STATE_RST = 0x0, 1846 MLX5_QPC_STATE_INIT = 0x1, 1847 MLX5_QPC_STATE_RTR = 0x2, 1848 MLX5_QPC_STATE_RTS = 0x3, 1849 MLX5_QPC_STATE_SQER = 0x4, 1850 MLX5_QPC_STATE_SQD = 0x5, 1851 MLX5_QPC_STATE_ERR = 0x6, 1852 MLX5_QPC_STATE_SUSPENDED = 0x9, 1853 }; 1854 1855 enum { 1856 MLX5_QPC_ST_RC = 0x0, 1857 MLX5_QPC_ST_UC = 0x1, 1858 MLX5_QPC_ST_UD = 0x2, 1859 MLX5_QPC_ST_XRC = 0x3, 1860 MLX5_QPC_ST_DCI = 0x5, 1861 MLX5_QPC_ST_QP0 = 0x7, 1862 MLX5_QPC_ST_QP1 = 0x8, 1863 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1864 MLX5_QPC_ST_REG_UMR = 0xc, 1865 }; 1866 1867 enum { 1868 MLX5_QP_PM_ARMED = 0x0, 1869 MLX5_QP_PM_REARM = 0x1, 1870 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1871 MLX5_QP_PM_MIGRATED = 0x3, 1872 }; 1873 1874 enum { 1875 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1876 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1877 }; 1878 1879 enum { 1880 MLX5_QPC_MTU_256_BYTES = 0x1, 1881 MLX5_QPC_MTU_512_BYTES = 0x2, 1882 MLX5_QPC_MTU_1K_BYTES = 0x3, 1883 MLX5_QPC_MTU_2K_BYTES = 0x4, 1884 MLX5_QPC_MTU_4K_BYTES = 0x5, 1885 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1886 }; 1887 1888 enum { 1889 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1890 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1891 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1892 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1893 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1894 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1895 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1896 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1897 }; 1898 1899 enum { 1900 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1901 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1902 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1903 }; 1904 1905 enum { 1906 MLX5_QPC_CS_RES_DISABLE = 0x0, 1907 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1908 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1909 }; 1910 1911 struct mlx5_ifc_qpc_bits { 1912 u8 state[0x4]; 1913 u8 lag_tx_port_affinity[0x4]; 1914 u8 st[0x8]; 1915 u8 reserved_1[0x3]; 1916 u8 pm_state[0x2]; 1917 u8 reserved_2[0x7]; 1918 u8 end_padding_mode[0x2]; 1919 u8 reserved_3[0x2]; 1920 1921 u8 wq_signature[0x1]; 1922 u8 block_lb_mc[0x1]; 1923 u8 atomic_like_write_en[0x1]; 1924 u8 latency_sensitive[0x1]; 1925 u8 reserved_4[0x1]; 1926 u8 drain_sigerr[0x1]; 1927 u8 reserved_5[0x2]; 1928 u8 pd[0x18]; 1929 1930 u8 mtu[0x3]; 1931 u8 log_msg_max[0x5]; 1932 u8 reserved_6[0x1]; 1933 u8 log_rq_size[0x4]; 1934 u8 log_rq_stride[0x3]; 1935 u8 no_sq[0x1]; 1936 u8 log_sq_size[0x4]; 1937 u8 reserved_7[0x6]; 1938 u8 rlky[0x1]; 1939 u8 ulp_stateless_offload_mode[0x4]; 1940 1941 u8 counter_set_id[0x8]; 1942 u8 uar_page[0x18]; 1943 1944 u8 reserved_8[0x8]; 1945 u8 user_index[0x18]; 1946 1947 u8 reserved_9[0x3]; 1948 u8 log_page_size[0x5]; 1949 u8 remote_qpn[0x18]; 1950 1951 struct mlx5_ifc_ads_bits primary_address_path; 1952 1953 struct mlx5_ifc_ads_bits secondary_address_path; 1954 1955 u8 log_ack_req_freq[0x4]; 1956 u8 reserved_10[0x4]; 1957 u8 log_sra_max[0x3]; 1958 u8 reserved_11[0x2]; 1959 u8 retry_count[0x3]; 1960 u8 rnr_retry[0x3]; 1961 u8 reserved_12[0x1]; 1962 u8 fre[0x1]; 1963 u8 cur_rnr_retry[0x3]; 1964 u8 cur_retry_count[0x3]; 1965 u8 reserved_13[0x5]; 1966 1967 u8 reserved_14[0x20]; 1968 1969 u8 reserved_15[0x8]; 1970 u8 next_send_psn[0x18]; 1971 1972 u8 reserved_16[0x8]; 1973 u8 cqn_snd[0x18]; 1974 1975 u8 reserved_at_400[0x8]; 1976 1977 u8 deth_sqpn[0x18]; 1978 u8 reserved_17[0x20]; 1979 1980 u8 reserved_18[0x8]; 1981 u8 last_acked_psn[0x18]; 1982 1983 u8 reserved_19[0x8]; 1984 u8 ssn[0x18]; 1985 1986 u8 reserved_20[0x8]; 1987 u8 log_rra_max[0x3]; 1988 u8 reserved_21[0x1]; 1989 u8 atomic_mode[0x4]; 1990 u8 rre[0x1]; 1991 u8 rwe[0x1]; 1992 u8 rae[0x1]; 1993 u8 reserved_22[0x1]; 1994 u8 page_offset[0x6]; 1995 u8 reserved_23[0x3]; 1996 u8 cd_slave_receive[0x1]; 1997 u8 cd_slave_send[0x1]; 1998 u8 cd_master[0x1]; 1999 2000 u8 reserved_24[0x3]; 2001 u8 min_rnr_nak[0x5]; 2002 u8 next_rcv_psn[0x18]; 2003 2004 u8 reserved_25[0x8]; 2005 u8 xrcd[0x18]; 2006 2007 u8 reserved_26[0x8]; 2008 u8 cqn_rcv[0x18]; 2009 2010 u8 dbr_addr[0x40]; 2011 2012 u8 q_key[0x20]; 2013 2014 u8 reserved_27[0x5]; 2015 u8 rq_type[0x3]; 2016 u8 srqn_rmpn[0x18]; 2017 2018 u8 reserved_28[0x8]; 2019 u8 rmsn[0x18]; 2020 2021 u8 hw_sq_wqebb_counter[0x10]; 2022 u8 sw_sq_wqebb_counter[0x10]; 2023 2024 u8 hw_rq_counter[0x20]; 2025 2026 u8 sw_rq_counter[0x20]; 2027 2028 u8 reserved_29[0x20]; 2029 2030 u8 reserved_30[0xf]; 2031 u8 cgs[0x1]; 2032 u8 cs_req[0x8]; 2033 u8 cs_res[0x8]; 2034 2035 u8 dc_access_key[0x40]; 2036 2037 u8 rdma_active[0x1]; 2038 u8 comm_est[0x1]; 2039 u8 suspended[0x1]; 2040 u8 reserved_31[0x5]; 2041 u8 send_msg_psn[0x18]; 2042 2043 u8 reserved_32[0x8]; 2044 u8 rcv_msg_psn[0x18]; 2045 2046 u8 rdma_va[0x40]; 2047 2048 u8 rdma_key[0x20]; 2049 2050 u8 reserved_33[0x20]; 2051 }; 2052 2053 struct mlx5_ifc_roce_addr_layout_bits { 2054 u8 source_l3_address[16][0x8]; 2055 2056 u8 reserved_0[0x3]; 2057 u8 vlan_valid[0x1]; 2058 u8 vlan_id[0xc]; 2059 u8 source_mac_47_32[0x10]; 2060 2061 u8 source_mac_31_0[0x20]; 2062 2063 u8 reserved_1[0x14]; 2064 u8 roce_l3_type[0x4]; 2065 u8 roce_version[0x8]; 2066 2067 u8 reserved_2[0x20]; 2068 }; 2069 2070 struct mlx5_ifc_rdbc_bits { 2071 u8 reserved_0[0x1c]; 2072 u8 type[0x4]; 2073 2074 u8 reserved_1[0x20]; 2075 2076 u8 reserved_2[0x8]; 2077 u8 psn[0x18]; 2078 2079 u8 rkey[0x20]; 2080 2081 u8 address[0x40]; 2082 2083 u8 byte_count[0x20]; 2084 2085 u8 reserved_3[0x20]; 2086 2087 u8 atomic_resp[32][0x8]; 2088 }; 2089 2090 enum { 2091 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2092 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2093 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2094 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2095 }; 2096 2097 struct mlx5_ifc_flow_context_bits { 2098 u8 reserved_0[0x20]; 2099 2100 u8 group_id[0x20]; 2101 2102 u8 reserved_1[0x8]; 2103 u8 flow_tag[0x18]; 2104 2105 u8 reserved_2[0x10]; 2106 u8 action[0x10]; 2107 2108 u8 reserved_3[0x8]; 2109 u8 destination_list_size[0x18]; 2110 2111 u8 reserved_4[0x8]; 2112 u8 flow_counter_list_size[0x18]; 2113 2114 u8 reserved_5[0x140]; 2115 2116 struct mlx5_ifc_fte_match_param_bits match_value; 2117 2118 u8 reserved_6[0x600]; 2119 2120 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2121 }; 2122 2123 enum { 2124 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2125 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2126 }; 2127 2128 struct mlx5_ifc_xrc_srqc_bits { 2129 u8 state[0x4]; 2130 u8 log_xrc_srq_size[0x4]; 2131 u8 reserved_0[0x18]; 2132 2133 u8 wq_signature[0x1]; 2134 u8 cont_srq[0x1]; 2135 u8 reserved_1[0x1]; 2136 u8 rlky[0x1]; 2137 u8 basic_cyclic_rcv_wqe[0x1]; 2138 u8 log_rq_stride[0x3]; 2139 u8 xrcd[0x18]; 2140 2141 u8 page_offset[0x6]; 2142 u8 reserved_2[0x2]; 2143 u8 cqn[0x18]; 2144 2145 u8 reserved_3[0x20]; 2146 2147 u8 reserved_4[0x2]; 2148 u8 log_page_size[0x6]; 2149 u8 user_index[0x18]; 2150 2151 u8 reserved_5[0x20]; 2152 2153 u8 reserved_6[0x8]; 2154 u8 pd[0x18]; 2155 2156 u8 lwm[0x10]; 2157 u8 wqe_cnt[0x10]; 2158 2159 u8 reserved_7[0x40]; 2160 2161 u8 db_record_addr_h[0x20]; 2162 2163 u8 db_record_addr_l[0x1e]; 2164 u8 reserved_8[0x2]; 2165 2166 u8 reserved_9[0x80]; 2167 }; 2168 2169 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2170 u8 counter_error_queues[0x20]; 2171 2172 u8 total_error_queues[0x20]; 2173 2174 u8 send_queue_priority_update_flow[0x20]; 2175 2176 u8 reserved_at_60[0x20]; 2177 2178 u8 nic_receive_steering_discard[0x40]; 2179 2180 u8 receive_discard_vport_down[0x40]; 2181 2182 u8 transmit_discard_vport_down[0x40]; 2183 2184 u8 reserved_at_140[0xec0]; 2185 }; 2186 2187 struct mlx5_ifc_traffic_counter_bits { 2188 u8 packets[0x40]; 2189 2190 u8 octets[0x40]; 2191 }; 2192 2193 struct mlx5_ifc_tisc_bits { 2194 u8 strict_lag_tx_port_affinity[0x1]; 2195 u8 reserved_at_1[0x3]; 2196 u8 lag_tx_port_affinity[0x04]; 2197 2198 u8 reserved_at_8[0x4]; 2199 u8 prio[0x4]; 2200 u8 reserved_1[0x10]; 2201 2202 u8 reserved_2[0x100]; 2203 2204 u8 reserved_3[0x8]; 2205 u8 transport_domain[0x18]; 2206 2207 u8 reserved_4[0x8]; 2208 u8 underlay_qpn[0x18]; 2209 2210 u8 reserved_5[0x3a0]; 2211 }; 2212 2213 enum { 2214 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2215 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2216 }; 2217 2218 enum { 2219 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2220 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2221 }; 2222 2223 enum { 2224 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2225 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2226 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2227 }; 2228 2229 enum { 2230 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2231 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2232 }; 2233 2234 struct mlx5_ifc_tirc_bits { 2235 u8 reserved_0[0x20]; 2236 2237 u8 disp_type[0x4]; 2238 u8 reserved_1[0x1c]; 2239 2240 u8 reserved_2[0x40]; 2241 2242 u8 reserved_3[0x4]; 2243 u8 lro_timeout_period_usecs[0x10]; 2244 u8 lro_enable_mask[0x4]; 2245 u8 lro_max_msg_sz[0x8]; 2246 2247 u8 reserved_4[0x40]; 2248 2249 u8 reserved_5[0x8]; 2250 u8 inline_rqn[0x18]; 2251 2252 u8 rx_hash_symmetric[0x1]; 2253 u8 reserved_6[0x1]; 2254 u8 tunneled_offload_en[0x1]; 2255 u8 reserved_7[0x5]; 2256 u8 indirect_table[0x18]; 2257 2258 u8 rx_hash_fn[0x4]; 2259 u8 reserved_8[0x2]; 2260 u8 self_lb_en[0x2]; 2261 u8 transport_domain[0x18]; 2262 2263 u8 rx_hash_toeplitz_key[10][0x20]; 2264 2265 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2266 2267 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2268 2269 u8 reserved_9[0x4c0]; 2270 }; 2271 2272 enum { 2273 MLX5_SRQC_STATE_GOOD = 0x0, 2274 MLX5_SRQC_STATE_ERROR = 0x1, 2275 }; 2276 2277 struct mlx5_ifc_srqc_bits { 2278 u8 state[0x4]; 2279 u8 log_srq_size[0x4]; 2280 u8 reserved_0[0x18]; 2281 2282 u8 wq_signature[0x1]; 2283 u8 cont_srq[0x1]; 2284 u8 reserved_1[0x1]; 2285 u8 rlky[0x1]; 2286 u8 reserved_2[0x1]; 2287 u8 log_rq_stride[0x3]; 2288 u8 xrcd[0x18]; 2289 2290 u8 page_offset[0x6]; 2291 u8 reserved_3[0x2]; 2292 u8 cqn[0x18]; 2293 2294 u8 reserved_4[0x20]; 2295 2296 u8 reserved_5[0x2]; 2297 u8 log_page_size[0x6]; 2298 u8 reserved_6[0x18]; 2299 2300 u8 reserved_7[0x20]; 2301 2302 u8 reserved_8[0x8]; 2303 u8 pd[0x18]; 2304 2305 u8 lwm[0x10]; 2306 u8 wqe_cnt[0x10]; 2307 2308 u8 reserved_9[0x40]; 2309 2310 u8 dbr_addr[0x40]; 2311 2312 u8 reserved_10[0x80]; 2313 }; 2314 2315 enum { 2316 MLX5_SQC_STATE_RST = 0x0, 2317 MLX5_SQC_STATE_RDY = 0x1, 2318 MLX5_SQC_STATE_ERR = 0x3, 2319 }; 2320 2321 struct mlx5_ifc_sqc_bits { 2322 u8 rlkey[0x1]; 2323 u8 cd_master[0x1]; 2324 u8 fre[0x1]; 2325 u8 flush_in_error_en[0x1]; 2326 u8 allow_multi_pkt_send_wqe[0x1]; 2327 u8 min_wqe_inline_mode[0x3]; 2328 u8 state[0x4]; 2329 u8 reg_umr[0x1]; 2330 u8 allow_swp[0x1]; 2331 u8 reserved_0[0x12]; 2332 2333 u8 reserved_1[0x8]; 2334 u8 user_index[0x18]; 2335 2336 u8 reserved_2[0x8]; 2337 u8 cqn[0x18]; 2338 2339 u8 reserved_3[0x80]; 2340 2341 u8 qos_para_vport_number[0x10]; 2342 u8 packet_pacing_rate_limit_index[0x10]; 2343 2344 u8 tis_lst_sz[0x10]; 2345 u8 reserved_4[0x10]; 2346 2347 u8 reserved_5[0x40]; 2348 2349 u8 reserved_6[0x8]; 2350 u8 tis_num_0[0x18]; 2351 2352 struct mlx5_ifc_wq_bits wq; 2353 }; 2354 2355 enum { 2356 MLX5_TSAR_TYPE_DWRR = 0, 2357 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2358 MLX5_TSAR_TYPE_ETS = 2 2359 }; 2360 2361 struct mlx5_ifc_tsar_element_attributes_bits { 2362 u8 reserved_0[0x8]; 2363 u8 tsar_type[0x8]; 2364 u8 reserved_1[0x10]; 2365 }; 2366 2367 struct mlx5_ifc_vport_element_attributes_bits { 2368 u8 reserved_0[0x10]; 2369 u8 vport_number[0x10]; 2370 }; 2371 2372 struct mlx5_ifc_vport_tc_element_attributes_bits { 2373 u8 traffic_class[0x10]; 2374 u8 vport_number[0x10]; 2375 }; 2376 2377 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2378 u8 reserved_0[0x0C]; 2379 u8 traffic_class[0x04]; 2380 u8 qos_para_vport_number[0x10]; 2381 }; 2382 2383 enum { 2384 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2385 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2386 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2387 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2388 }; 2389 2390 struct mlx5_ifc_scheduling_context_bits { 2391 u8 element_type[0x8]; 2392 u8 reserved_at_8[0x18]; 2393 2394 u8 element_attributes[0x20]; 2395 2396 u8 parent_element_id[0x20]; 2397 2398 u8 reserved_at_60[0x40]; 2399 2400 u8 bw_share[0x20]; 2401 2402 u8 max_average_bw[0x20]; 2403 2404 u8 reserved_at_e0[0x120]; 2405 }; 2406 2407 struct mlx5_ifc_rqtc_bits { 2408 u8 reserved_0[0xa0]; 2409 2410 u8 reserved_1[0x10]; 2411 u8 rqt_max_size[0x10]; 2412 2413 u8 reserved_2[0x10]; 2414 u8 rqt_actual_size[0x10]; 2415 2416 u8 reserved_3[0x6a0]; 2417 2418 struct mlx5_ifc_rq_num_bits rq_num[0]; 2419 }; 2420 2421 enum { 2422 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2423 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2424 }; 2425 2426 enum { 2427 MLX5_RQC_STATE_RST = 0x0, 2428 MLX5_RQC_STATE_RDY = 0x1, 2429 MLX5_RQC_STATE_ERR = 0x3, 2430 }; 2431 2432 enum { 2433 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2434 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2435 }; 2436 2437 struct mlx5_ifc_rqc_bits { 2438 u8 rlkey[0x1]; 2439 u8 delay_drop_en[0x1]; 2440 u8 scatter_fcs[0x1]; 2441 u8 vlan_strip_disable[0x1]; 2442 u8 mem_rq_type[0x4]; 2443 u8 state[0x4]; 2444 u8 reserved_1[0x1]; 2445 u8 flush_in_error_en[0x1]; 2446 u8 reserved_2[0x12]; 2447 2448 u8 reserved_3[0x8]; 2449 u8 user_index[0x18]; 2450 2451 u8 reserved_4[0x8]; 2452 u8 cqn[0x18]; 2453 2454 u8 counter_set_id[0x8]; 2455 u8 reserved_5[0x18]; 2456 2457 u8 reserved_6[0x8]; 2458 u8 rmpn[0x18]; 2459 2460 u8 reserved_7[0xe0]; 2461 2462 struct mlx5_ifc_wq_bits wq; 2463 }; 2464 2465 enum { 2466 MLX5_RMPC_STATE_RDY = 0x1, 2467 MLX5_RMPC_STATE_ERR = 0x3, 2468 }; 2469 2470 struct mlx5_ifc_rmpc_bits { 2471 u8 reserved_0[0x8]; 2472 u8 state[0x4]; 2473 u8 reserved_1[0x14]; 2474 2475 u8 basic_cyclic_rcv_wqe[0x1]; 2476 u8 reserved_2[0x1f]; 2477 2478 u8 reserved_3[0x140]; 2479 2480 struct mlx5_ifc_wq_bits wq; 2481 }; 2482 2483 enum { 2484 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2485 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2486 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2487 }; 2488 2489 struct mlx5_ifc_nic_vport_context_bits { 2490 u8 reserved_0[0x5]; 2491 u8 min_wqe_inline_mode[0x3]; 2492 u8 reserved_1[0x15]; 2493 u8 disable_mc_local_lb[0x1]; 2494 u8 disable_uc_local_lb[0x1]; 2495 u8 roce_en[0x1]; 2496 2497 u8 arm_change_event[0x1]; 2498 u8 reserved_2[0x1a]; 2499 u8 event_on_mtu[0x1]; 2500 u8 event_on_promisc_change[0x1]; 2501 u8 event_on_vlan_change[0x1]; 2502 u8 event_on_mc_address_change[0x1]; 2503 u8 event_on_uc_address_change[0x1]; 2504 2505 u8 reserved_3[0xe0]; 2506 2507 u8 reserved_4[0x10]; 2508 u8 mtu[0x10]; 2509 2510 u8 system_image_guid[0x40]; 2511 2512 u8 port_guid[0x40]; 2513 2514 u8 node_guid[0x40]; 2515 2516 u8 reserved_5[0x140]; 2517 2518 u8 qkey_violation_counter[0x10]; 2519 u8 reserved_6[0x10]; 2520 2521 u8 reserved_7[0x420]; 2522 2523 u8 promisc_uc[0x1]; 2524 u8 promisc_mc[0x1]; 2525 u8 promisc_all[0x1]; 2526 u8 reserved_8[0x2]; 2527 u8 allowed_list_type[0x3]; 2528 u8 reserved_9[0xc]; 2529 u8 allowed_list_size[0xc]; 2530 2531 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2532 2533 u8 reserved_10[0x20]; 2534 2535 u8 current_uc_mac_address[0][0x40]; 2536 }; 2537 2538 enum { 2539 MLX5_ACCESS_MODE_PA = 0x0, 2540 MLX5_ACCESS_MODE_MTT = 0x1, 2541 MLX5_ACCESS_MODE_KLM = 0x2, 2542 }; 2543 2544 struct mlx5_ifc_mkc_bits { 2545 u8 reserved_at_0[0x1]; 2546 u8 free[0x1]; 2547 u8 reserved_at_2[0x1]; 2548 u8 access_mode_4_2[0x3]; 2549 u8 reserved_at_6[0x7]; 2550 u8 relaxed_ordering_write[0x1]; 2551 u8 reserved_at_e[0x1]; 2552 u8 small_fence_on_rdma_read_response[0x1]; 2553 u8 umr_en[0x1]; 2554 u8 a[0x1]; 2555 u8 rw[0x1]; 2556 u8 rr[0x1]; 2557 u8 lw[0x1]; 2558 u8 lr[0x1]; 2559 u8 access_mode[0x2]; 2560 u8 reserved_2[0x8]; 2561 2562 u8 qpn[0x18]; 2563 u8 mkey_7_0[0x8]; 2564 2565 u8 reserved_3[0x20]; 2566 2567 u8 length64[0x1]; 2568 u8 bsf_en[0x1]; 2569 u8 sync_umr[0x1]; 2570 u8 reserved_4[0x2]; 2571 u8 expected_sigerr_count[0x1]; 2572 u8 reserved_5[0x1]; 2573 u8 en_rinval[0x1]; 2574 u8 pd[0x18]; 2575 2576 u8 start_addr[0x40]; 2577 2578 u8 len[0x40]; 2579 2580 u8 bsf_octword_size[0x20]; 2581 2582 u8 reserved_6[0x80]; 2583 2584 u8 translations_octword_size[0x20]; 2585 2586 u8 reserved_7[0x1b]; 2587 u8 log_page_size[0x5]; 2588 2589 u8 reserved_8[0x20]; 2590 }; 2591 2592 struct mlx5_ifc_pkey_bits { 2593 u8 reserved_0[0x10]; 2594 u8 pkey[0x10]; 2595 }; 2596 2597 struct mlx5_ifc_array128_auto_bits { 2598 u8 array128_auto[16][0x8]; 2599 }; 2600 2601 enum { 2602 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2603 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2604 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2605 }; 2606 2607 enum { 2608 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2609 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2610 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2611 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2612 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2613 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2614 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2615 }; 2616 2617 enum { 2618 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2619 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2620 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2621 }; 2622 2623 enum { 2624 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2625 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2626 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2627 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2628 }; 2629 2630 enum { 2631 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2632 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2633 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2634 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2635 }; 2636 2637 struct mlx5_ifc_hca_vport_context_bits { 2638 u8 field_select[0x20]; 2639 2640 u8 reserved_0[0xe0]; 2641 2642 u8 sm_virt_aware[0x1]; 2643 u8 has_smi[0x1]; 2644 u8 has_raw[0x1]; 2645 u8 grh_required[0x1]; 2646 u8 reserved_1[0x1]; 2647 u8 min_wqe_inline_mode[0x3]; 2648 u8 reserved_2[0x8]; 2649 u8 port_physical_state[0x4]; 2650 u8 vport_state_policy[0x4]; 2651 u8 port_state[0x4]; 2652 u8 vport_state[0x4]; 2653 2654 u8 reserved_3[0x20]; 2655 2656 u8 system_image_guid[0x40]; 2657 2658 u8 port_guid[0x40]; 2659 2660 u8 node_guid[0x40]; 2661 2662 u8 cap_mask1[0x20]; 2663 2664 u8 cap_mask1_field_select[0x20]; 2665 2666 u8 cap_mask2[0x20]; 2667 2668 u8 cap_mask2_field_select[0x20]; 2669 2670 u8 reserved_4[0x80]; 2671 2672 u8 lid[0x10]; 2673 u8 reserved_5[0x4]; 2674 u8 init_type_reply[0x4]; 2675 u8 lmc[0x3]; 2676 u8 subnet_timeout[0x5]; 2677 2678 u8 sm_lid[0x10]; 2679 u8 sm_sl[0x4]; 2680 u8 reserved_6[0xc]; 2681 2682 u8 qkey_violation_counter[0x10]; 2683 u8 pkey_violation_counter[0x10]; 2684 2685 u8 reserved_7[0xca0]; 2686 }; 2687 2688 union mlx5_ifc_hca_cap_union_bits { 2689 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2690 struct mlx5_ifc_odp_cap_bits odp_cap; 2691 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2692 struct mlx5_ifc_roce_cap_bits roce_cap; 2693 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2694 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2695 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2696 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2697 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2698 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2699 struct mlx5_ifc_qos_cap_bits qos_cap; 2700 u8 reserved_0[0x8000]; 2701 }; 2702 2703 enum { 2704 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2705 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2706 }; 2707 2708 struct mlx5_ifc_flow_table_context_bits { 2709 u8 encap_en[0x1]; 2710 u8 decap_en[0x1]; 2711 u8 reserved_at_2[0x2]; 2712 u8 table_miss_action[0x4]; 2713 u8 level[0x8]; 2714 u8 reserved_at_10[0x8]; 2715 u8 log_size[0x8]; 2716 2717 u8 reserved_at_20[0x8]; 2718 u8 table_miss_id[0x18]; 2719 2720 u8 reserved_at_40[0x8]; 2721 u8 lag_master_next_table_id[0x18]; 2722 2723 u8 reserved_at_60[0xe0]; 2724 }; 2725 2726 struct mlx5_ifc_esw_vport_context_bits { 2727 u8 reserved_0[0x3]; 2728 u8 vport_svlan_strip[0x1]; 2729 u8 vport_cvlan_strip[0x1]; 2730 u8 vport_svlan_insert[0x1]; 2731 u8 vport_cvlan_insert[0x2]; 2732 u8 reserved_1[0x18]; 2733 2734 u8 reserved_2[0x20]; 2735 2736 u8 svlan_cfi[0x1]; 2737 u8 svlan_pcp[0x3]; 2738 u8 svlan_id[0xc]; 2739 u8 cvlan_cfi[0x1]; 2740 u8 cvlan_pcp[0x3]; 2741 u8 cvlan_id[0xc]; 2742 2743 u8 reserved_3[0x7a0]; 2744 }; 2745 2746 enum { 2747 MLX5_EQC_STATUS_OK = 0x0, 2748 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2749 }; 2750 2751 enum { 2752 MLX5_EQ_STATE_ARMED = 0x9, 2753 MLX5_EQ_STATE_FIRED = 0xa, 2754 }; 2755 2756 struct mlx5_ifc_eqc_bits { 2757 u8 status[0x4]; 2758 u8 reserved_0[0x9]; 2759 u8 ec[0x1]; 2760 u8 oi[0x1]; 2761 u8 reserved_1[0x5]; 2762 u8 st[0x4]; 2763 u8 reserved_2[0x8]; 2764 2765 u8 reserved_3[0x20]; 2766 2767 u8 reserved_4[0x14]; 2768 u8 page_offset[0x6]; 2769 u8 reserved_5[0x6]; 2770 2771 u8 reserved_6[0x3]; 2772 u8 log_eq_size[0x5]; 2773 u8 uar_page[0x18]; 2774 2775 u8 reserved_7[0x20]; 2776 2777 u8 reserved_8[0x18]; 2778 u8 intr[0x8]; 2779 2780 u8 reserved_9[0x3]; 2781 u8 log_page_size[0x5]; 2782 u8 reserved_10[0x18]; 2783 2784 u8 reserved_11[0x60]; 2785 2786 u8 reserved_12[0x8]; 2787 u8 consumer_counter[0x18]; 2788 2789 u8 reserved_13[0x8]; 2790 u8 producer_counter[0x18]; 2791 2792 u8 reserved_14[0x80]; 2793 }; 2794 2795 enum { 2796 MLX5_DCTC_STATE_ACTIVE = 0x0, 2797 MLX5_DCTC_STATE_DRAINING = 0x1, 2798 MLX5_DCTC_STATE_DRAINED = 0x2, 2799 }; 2800 2801 enum { 2802 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2803 MLX5_DCTC_CS_RES_NA = 0x1, 2804 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2805 }; 2806 2807 enum { 2808 MLX5_DCTC_MTU_256_BYTES = 0x1, 2809 MLX5_DCTC_MTU_512_BYTES = 0x2, 2810 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2811 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2812 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2813 }; 2814 2815 struct mlx5_ifc_dctc_bits { 2816 u8 reserved_0[0x4]; 2817 u8 state[0x4]; 2818 u8 reserved_1[0x18]; 2819 2820 u8 reserved_2[0x8]; 2821 u8 user_index[0x18]; 2822 2823 u8 reserved_3[0x8]; 2824 u8 cqn[0x18]; 2825 2826 u8 counter_set_id[0x8]; 2827 u8 atomic_mode[0x4]; 2828 u8 rre[0x1]; 2829 u8 rwe[0x1]; 2830 u8 rae[0x1]; 2831 u8 atomic_like_write_en[0x1]; 2832 u8 latency_sensitive[0x1]; 2833 u8 rlky[0x1]; 2834 u8 reserved_4[0xe]; 2835 2836 u8 reserved_5[0x8]; 2837 u8 cs_res[0x8]; 2838 u8 reserved_6[0x3]; 2839 u8 min_rnr_nak[0x5]; 2840 u8 reserved_7[0x8]; 2841 2842 u8 reserved_8[0x8]; 2843 u8 srqn[0x18]; 2844 2845 u8 reserved_9[0x8]; 2846 u8 pd[0x18]; 2847 2848 u8 tclass[0x8]; 2849 u8 reserved_10[0x4]; 2850 u8 flow_label[0x14]; 2851 2852 u8 dc_access_key[0x40]; 2853 2854 u8 reserved_11[0x5]; 2855 u8 mtu[0x3]; 2856 u8 port[0x8]; 2857 u8 pkey_index[0x10]; 2858 2859 u8 reserved_12[0x8]; 2860 u8 my_addr_index[0x8]; 2861 u8 reserved_13[0x8]; 2862 u8 hop_limit[0x8]; 2863 2864 u8 dc_access_key_violation_count[0x20]; 2865 2866 u8 reserved_14[0x14]; 2867 u8 dei_cfi[0x1]; 2868 u8 eth_prio[0x3]; 2869 u8 ecn[0x2]; 2870 u8 dscp[0x6]; 2871 2872 u8 reserved_15[0x40]; 2873 }; 2874 2875 enum { 2876 MLX5_CQC_STATUS_OK = 0x0, 2877 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2878 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2879 }; 2880 2881 enum { 2882 CQE_SIZE_64 = 0x0, 2883 CQE_SIZE_128 = 0x1, 2884 }; 2885 2886 enum { 2887 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2888 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2889 }; 2890 2891 enum { 2892 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2893 MLX5_CQ_STATE_ARMED = 0x9, 2894 MLX5_CQ_STATE_FIRED = 0xa, 2895 }; 2896 2897 struct mlx5_ifc_cqc_bits { 2898 u8 status[0x4]; 2899 u8 reserved_0[0x4]; 2900 u8 cqe_sz[0x3]; 2901 u8 cc[0x1]; 2902 u8 reserved_1[0x1]; 2903 u8 scqe_break_moderation_en[0x1]; 2904 u8 oi[0x1]; 2905 u8 cq_period_mode[0x2]; 2906 u8 cqe_compression_en[0x1]; 2907 u8 mini_cqe_res_format[0x2]; 2908 u8 st[0x4]; 2909 u8 reserved_2[0x8]; 2910 2911 u8 reserved_3[0x20]; 2912 2913 u8 reserved_4[0x14]; 2914 u8 page_offset[0x6]; 2915 u8 reserved_5[0x6]; 2916 2917 u8 reserved_6[0x3]; 2918 u8 log_cq_size[0x5]; 2919 u8 uar_page[0x18]; 2920 2921 u8 reserved_7[0x4]; 2922 u8 cq_period[0xc]; 2923 u8 cq_max_count[0x10]; 2924 2925 u8 reserved_8[0x18]; 2926 u8 c_eqn[0x8]; 2927 2928 u8 reserved_9[0x3]; 2929 u8 log_page_size[0x5]; 2930 u8 reserved_10[0x18]; 2931 2932 u8 reserved_11[0x20]; 2933 2934 u8 reserved_12[0x8]; 2935 u8 last_notified_index[0x18]; 2936 2937 u8 reserved_13[0x8]; 2938 u8 last_solicit_index[0x18]; 2939 2940 u8 reserved_14[0x8]; 2941 u8 consumer_counter[0x18]; 2942 2943 u8 reserved_15[0x8]; 2944 u8 producer_counter[0x18]; 2945 2946 u8 reserved_16[0x40]; 2947 2948 u8 dbr_addr[0x40]; 2949 }; 2950 2951 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2952 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2953 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2954 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2955 u8 reserved_0[0x800]; 2956 }; 2957 2958 struct mlx5_ifc_query_adapter_param_block_bits { 2959 u8 reserved_0[0xc0]; 2960 2961 u8 reserved_1[0x8]; 2962 u8 ieee_vendor_id[0x18]; 2963 2964 u8 reserved_2[0x10]; 2965 u8 vsd_vendor_id[0x10]; 2966 2967 u8 vsd[208][0x8]; 2968 2969 u8 vsd_contd_psid[16][0x8]; 2970 }; 2971 2972 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2973 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2974 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2975 u8 reserved_0[0x20]; 2976 }; 2977 2978 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2979 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2980 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2981 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2982 u8 reserved_0[0x20]; 2983 }; 2984 2985 struct mlx5_ifc_bufferx_reg_bits { 2986 u8 reserved_0[0x6]; 2987 u8 lossy[0x1]; 2988 u8 epsb[0x1]; 2989 u8 reserved_1[0xc]; 2990 u8 size[0xc]; 2991 2992 u8 xoff_threshold[0x10]; 2993 u8 xon_threshold[0x10]; 2994 }; 2995 2996 struct mlx5_ifc_config_item_bits { 2997 u8 valid[0x2]; 2998 u8 reserved_0[0x2]; 2999 u8 header_type[0x2]; 3000 u8 reserved_1[0x2]; 3001 u8 default_location[0x1]; 3002 u8 reserved_2[0x7]; 3003 u8 version[0x4]; 3004 u8 reserved_3[0x3]; 3005 u8 length[0x9]; 3006 3007 u8 type[0x20]; 3008 3009 u8 reserved_4[0x10]; 3010 u8 crc16[0x10]; 3011 }; 3012 3013 struct mlx5_ifc_nodnic_port_config_reg_bits { 3014 struct mlx5_ifc_nodnic_event_word_bits event; 3015 3016 u8 network_en[0x1]; 3017 u8 dma_en[0x1]; 3018 u8 promisc_en[0x1]; 3019 u8 promisc_multicast_en[0x1]; 3020 u8 reserved_0[0x17]; 3021 u8 receive_filter_en[0x5]; 3022 3023 u8 reserved_1[0x10]; 3024 u8 mac_47_32[0x10]; 3025 3026 u8 mac_31_0[0x20]; 3027 3028 u8 receive_filters_mgid_mac[64][0x8]; 3029 3030 u8 gid[16][0x8]; 3031 3032 u8 reserved_2[0x10]; 3033 u8 lid[0x10]; 3034 3035 u8 reserved_3[0xc]; 3036 u8 sm_sl[0x4]; 3037 u8 sm_lid[0x10]; 3038 3039 u8 completion_address_63_32[0x20]; 3040 3041 u8 completion_address_31_12[0x14]; 3042 u8 reserved_4[0x6]; 3043 u8 log_cq_size[0x6]; 3044 3045 u8 working_buffer_address_63_32[0x20]; 3046 3047 u8 working_buffer_address_31_12[0x14]; 3048 u8 reserved_5[0xc]; 3049 3050 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3051 3052 u8 pkey_index[0x10]; 3053 u8 pkey[0x10]; 3054 3055 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3056 3057 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3058 3059 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3060 3061 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3062 3063 u8 reserved_6[0x400]; 3064 }; 3065 3066 union mlx5_ifc_event_auto_bits { 3067 struct mlx5_ifc_comp_event_bits comp_event; 3068 struct mlx5_ifc_dct_events_bits dct_events; 3069 struct mlx5_ifc_qp_events_bits qp_events; 3070 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3071 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3072 struct mlx5_ifc_cq_error_bits cq_error; 3073 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3074 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3075 struct mlx5_ifc_gpio_event_bits gpio_event; 3076 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3077 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3078 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3079 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3080 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3081 u8 reserved_0[0xe0]; 3082 }; 3083 3084 struct mlx5_ifc_health_buffer_bits { 3085 u8 reserved_0[0x100]; 3086 3087 u8 assert_existptr[0x20]; 3088 3089 u8 assert_callra[0x20]; 3090 3091 u8 reserved_1[0x40]; 3092 3093 u8 fw_version[0x20]; 3094 3095 u8 hw_id[0x20]; 3096 3097 u8 reserved_2[0x20]; 3098 3099 u8 irisc_index[0x8]; 3100 u8 synd[0x8]; 3101 u8 ext_synd[0x10]; 3102 }; 3103 3104 struct mlx5_ifc_register_loopback_control_bits { 3105 u8 no_lb[0x1]; 3106 u8 reserved_0[0x7]; 3107 u8 port[0x8]; 3108 u8 reserved_1[0x10]; 3109 3110 u8 reserved_2[0x60]; 3111 }; 3112 3113 struct mlx5_ifc_lrh_bits { 3114 u8 vl[4]; 3115 u8 lver[4]; 3116 u8 sl[4]; 3117 u8 reserved2[2]; 3118 u8 lnh[2]; 3119 u8 dlid[16]; 3120 u8 reserved5[5]; 3121 u8 pkt_len[11]; 3122 u8 slid[16]; 3123 }; 3124 3125 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3126 u8 reserved_0[0x40]; 3127 3128 u8 reserved_1[0x10]; 3129 u8 rol_mode[0x8]; 3130 u8 wol_mode[0x8]; 3131 }; 3132 3133 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3134 u8 reserved_0[0x40]; 3135 3136 u8 rol_mode_valid[0x1]; 3137 u8 wol_mode_valid[0x1]; 3138 u8 reserved_1[0xe]; 3139 u8 rol_mode[0x8]; 3140 u8 wol_mode[0x8]; 3141 3142 u8 reserved_2[0x7a0]; 3143 }; 3144 3145 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3146 u8 virtual_mac_en[0x1]; 3147 u8 mac_aux_v[0x1]; 3148 u8 reserved_0[0x1e]; 3149 3150 u8 reserved_1[0x40]; 3151 3152 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3153 3154 u8 reserved_2[0x760]; 3155 }; 3156 3157 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3158 u8 virtual_mac_en[0x1]; 3159 u8 mac_aux_v[0x1]; 3160 u8 reserved_0[0x1e]; 3161 3162 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3163 3164 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3165 3166 u8 reserved_1[0x760]; 3167 }; 3168 3169 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3170 struct mlx5_ifc_fw_version_bits fw_version; 3171 3172 u8 reserved_0[0x10]; 3173 u8 hash_signature[0x10]; 3174 3175 u8 psid[16][0x8]; 3176 3177 u8 reserved_1[0x6e0]; 3178 }; 3179 3180 struct mlx5_ifc_icmd_query_cap_in_bits { 3181 u8 reserved_0[0x10]; 3182 u8 capability_group[0x10]; 3183 }; 3184 3185 struct mlx5_ifc_icmd_query_cap_general_bits { 3186 u8 nv_access[0x1]; 3187 u8 fw_info_psid[0x1]; 3188 u8 reserved_0[0x1e]; 3189 3190 u8 reserved_1[0x16]; 3191 u8 rol_s[0x1]; 3192 u8 rol_g[0x1]; 3193 u8 reserved_2[0x1]; 3194 u8 wol_s[0x1]; 3195 u8 wol_g[0x1]; 3196 u8 wol_a[0x1]; 3197 u8 wol_b[0x1]; 3198 u8 wol_m[0x1]; 3199 u8 wol_u[0x1]; 3200 u8 wol_p[0x1]; 3201 }; 3202 3203 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3204 u8 status[0x8]; 3205 u8 reserved_0[0x18]; 3206 3207 u8 reserved_1[0x7e0]; 3208 }; 3209 3210 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3211 u8 status[0x8]; 3212 u8 reserved_0[0x18]; 3213 3214 u8 reserved_1[0x7e0]; 3215 }; 3216 3217 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3218 u8 address_hi[0x20]; 3219 3220 u8 address_lo[0x20]; 3221 3222 u8 reserved_0[0x7c0]; 3223 }; 3224 3225 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3226 u8 reserved_0[0x20]; 3227 3228 u8 address_hi[0x20]; 3229 3230 u8 address_lo[0x20]; 3231 3232 u8 reserved_1[0x7a0]; 3233 }; 3234 3235 struct mlx5_ifc_icmd_access_reg_out_bits { 3236 u8 reserved_0[0x11]; 3237 u8 status[0x7]; 3238 u8 reserved_1[0x8]; 3239 3240 u8 register_id[0x10]; 3241 u8 reserved_2[0x10]; 3242 3243 u8 reserved_3[0x40]; 3244 3245 u8 reserved_4[0x5]; 3246 u8 len[0xb]; 3247 u8 reserved_5[0x10]; 3248 3249 u8 register_data[0][0x20]; 3250 }; 3251 3252 enum { 3253 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3254 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3255 }; 3256 3257 struct mlx5_ifc_icmd_access_reg_in_bits { 3258 u8 constant_1[0x5]; 3259 u8 constant_2[0xb]; 3260 u8 reserved_0[0x10]; 3261 3262 u8 register_id[0x10]; 3263 u8 reserved_1[0x1]; 3264 u8 method[0x7]; 3265 u8 constant_3[0x8]; 3266 3267 u8 reserved_2[0x40]; 3268 3269 u8 constant_4[0x5]; 3270 u8 len[0xb]; 3271 u8 reserved_3[0x10]; 3272 3273 u8 register_data[0][0x20]; 3274 }; 3275 3276 enum { 3277 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3278 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3279 }; 3280 3281 struct mlx5_ifc_teardown_hca_out_bits { 3282 u8 status[0x8]; 3283 u8 reserved_0[0x18]; 3284 3285 u8 syndrome[0x20]; 3286 3287 u8 reserved_1[0x3f]; 3288 3289 u8 state[0x1]; 3290 }; 3291 3292 enum { 3293 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3294 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3295 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3296 }; 3297 3298 struct mlx5_ifc_teardown_hca_in_bits { 3299 u8 opcode[0x10]; 3300 u8 reserved_0[0x10]; 3301 3302 u8 reserved_1[0x10]; 3303 u8 op_mod[0x10]; 3304 3305 u8 reserved_2[0x10]; 3306 u8 profile[0x10]; 3307 3308 u8 reserved_3[0x20]; 3309 }; 3310 3311 struct mlx5_ifc_set_delay_drop_params_out_bits { 3312 u8 status[0x8]; 3313 u8 reserved_at_8[0x18]; 3314 3315 u8 syndrome[0x20]; 3316 3317 u8 reserved_at_40[0x40]; 3318 }; 3319 3320 struct mlx5_ifc_set_delay_drop_params_in_bits { 3321 u8 opcode[0x10]; 3322 u8 reserved_at_10[0x10]; 3323 3324 u8 reserved_at_20[0x10]; 3325 u8 op_mod[0x10]; 3326 3327 u8 reserved_at_40[0x20]; 3328 3329 u8 reserved_at_60[0x10]; 3330 u8 delay_drop_timeout[0x10]; 3331 }; 3332 3333 struct mlx5_ifc_query_delay_drop_params_out_bits { 3334 u8 status[0x8]; 3335 u8 reserved_at_8[0x18]; 3336 3337 u8 syndrome[0x20]; 3338 3339 u8 reserved_at_40[0x20]; 3340 3341 u8 reserved_at_60[0x10]; 3342 u8 delay_drop_timeout[0x10]; 3343 }; 3344 3345 struct mlx5_ifc_query_delay_drop_params_in_bits { 3346 u8 opcode[0x10]; 3347 u8 reserved_at_10[0x10]; 3348 3349 u8 reserved_at_20[0x10]; 3350 u8 op_mod[0x10]; 3351 3352 u8 reserved_at_40[0x40]; 3353 }; 3354 3355 struct mlx5_ifc_suspend_qp_out_bits { 3356 u8 status[0x8]; 3357 u8 reserved_0[0x18]; 3358 3359 u8 syndrome[0x20]; 3360 3361 u8 reserved_1[0x40]; 3362 }; 3363 3364 struct mlx5_ifc_suspend_qp_in_bits { 3365 u8 opcode[0x10]; 3366 u8 reserved_0[0x10]; 3367 3368 u8 reserved_1[0x10]; 3369 u8 op_mod[0x10]; 3370 3371 u8 reserved_2[0x8]; 3372 u8 qpn[0x18]; 3373 3374 u8 reserved_3[0x20]; 3375 }; 3376 3377 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3378 u8 status[0x8]; 3379 u8 reserved_0[0x18]; 3380 3381 u8 syndrome[0x20]; 3382 3383 u8 reserved_1[0x40]; 3384 }; 3385 3386 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3387 u8 opcode[0x10]; 3388 u8 reserved_0[0x10]; 3389 3390 u8 reserved_1[0x10]; 3391 u8 op_mod[0x10]; 3392 3393 u8 reserved_2[0x8]; 3394 u8 qpn[0x18]; 3395 3396 u8 reserved_3[0x20]; 3397 3398 u8 opt_param_mask[0x20]; 3399 3400 u8 reserved_4[0x20]; 3401 3402 struct mlx5_ifc_qpc_bits qpc; 3403 3404 u8 reserved_5[0x80]; 3405 }; 3406 3407 struct mlx5_ifc_sqd2rts_qp_out_bits { 3408 u8 status[0x8]; 3409 u8 reserved_0[0x18]; 3410 3411 u8 syndrome[0x20]; 3412 3413 u8 reserved_1[0x40]; 3414 }; 3415 3416 struct mlx5_ifc_sqd2rts_qp_in_bits { 3417 u8 opcode[0x10]; 3418 u8 reserved_0[0x10]; 3419 3420 u8 reserved_1[0x10]; 3421 u8 op_mod[0x10]; 3422 3423 u8 reserved_2[0x8]; 3424 u8 qpn[0x18]; 3425 3426 u8 reserved_3[0x20]; 3427 3428 u8 opt_param_mask[0x20]; 3429 3430 u8 reserved_4[0x20]; 3431 3432 struct mlx5_ifc_qpc_bits qpc; 3433 3434 u8 reserved_5[0x80]; 3435 }; 3436 3437 struct mlx5_ifc_set_wol_rol_out_bits { 3438 u8 status[0x8]; 3439 u8 reserved_0[0x18]; 3440 3441 u8 syndrome[0x20]; 3442 3443 u8 reserved_1[0x40]; 3444 }; 3445 3446 struct mlx5_ifc_set_wol_rol_in_bits { 3447 u8 opcode[0x10]; 3448 u8 reserved_0[0x10]; 3449 3450 u8 reserved_1[0x10]; 3451 u8 op_mod[0x10]; 3452 3453 u8 rol_mode_valid[0x1]; 3454 u8 wol_mode_valid[0x1]; 3455 u8 reserved_2[0xe]; 3456 u8 rol_mode[0x8]; 3457 u8 wol_mode[0x8]; 3458 3459 u8 reserved_3[0x20]; 3460 }; 3461 3462 struct mlx5_ifc_set_roce_address_out_bits { 3463 u8 status[0x8]; 3464 u8 reserved_0[0x18]; 3465 3466 u8 syndrome[0x20]; 3467 3468 u8 reserved_1[0x40]; 3469 }; 3470 3471 struct mlx5_ifc_set_roce_address_in_bits { 3472 u8 opcode[0x10]; 3473 u8 reserved_0[0x10]; 3474 3475 u8 reserved_1[0x10]; 3476 u8 op_mod[0x10]; 3477 3478 u8 roce_address_index[0x10]; 3479 u8 reserved_2[0x10]; 3480 3481 u8 reserved_3[0x20]; 3482 3483 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3484 }; 3485 3486 struct mlx5_ifc_set_rdb_out_bits { 3487 u8 status[0x8]; 3488 u8 reserved_0[0x18]; 3489 3490 u8 syndrome[0x20]; 3491 3492 u8 reserved_1[0x40]; 3493 }; 3494 3495 struct mlx5_ifc_set_rdb_in_bits { 3496 u8 opcode[0x10]; 3497 u8 reserved_0[0x10]; 3498 3499 u8 reserved_1[0x10]; 3500 u8 op_mod[0x10]; 3501 3502 u8 reserved_2[0x8]; 3503 u8 qpn[0x18]; 3504 3505 u8 reserved_3[0x18]; 3506 u8 rdb_list_size[0x8]; 3507 3508 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3509 }; 3510 3511 struct mlx5_ifc_set_mad_demux_out_bits { 3512 u8 status[0x8]; 3513 u8 reserved_0[0x18]; 3514 3515 u8 syndrome[0x20]; 3516 3517 u8 reserved_1[0x40]; 3518 }; 3519 3520 enum { 3521 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3522 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3523 }; 3524 3525 struct mlx5_ifc_set_mad_demux_in_bits { 3526 u8 opcode[0x10]; 3527 u8 reserved_0[0x10]; 3528 3529 u8 reserved_1[0x10]; 3530 u8 op_mod[0x10]; 3531 3532 u8 reserved_2[0x20]; 3533 3534 u8 reserved_3[0x6]; 3535 u8 demux_mode[0x2]; 3536 u8 reserved_4[0x18]; 3537 }; 3538 3539 struct mlx5_ifc_set_l2_table_entry_out_bits { 3540 u8 status[0x8]; 3541 u8 reserved_0[0x18]; 3542 3543 u8 syndrome[0x20]; 3544 3545 u8 reserved_1[0x40]; 3546 }; 3547 3548 struct mlx5_ifc_set_l2_table_entry_in_bits { 3549 u8 opcode[0x10]; 3550 u8 reserved_0[0x10]; 3551 3552 u8 reserved_1[0x10]; 3553 u8 op_mod[0x10]; 3554 3555 u8 reserved_2[0x60]; 3556 3557 u8 reserved_3[0x8]; 3558 u8 table_index[0x18]; 3559 3560 u8 reserved_4[0x20]; 3561 3562 u8 reserved_5[0x13]; 3563 u8 vlan_valid[0x1]; 3564 u8 vlan[0xc]; 3565 3566 struct mlx5_ifc_mac_address_layout_bits mac_address; 3567 3568 u8 reserved_6[0xc0]; 3569 }; 3570 3571 struct mlx5_ifc_set_issi_out_bits { 3572 u8 status[0x8]; 3573 u8 reserved_0[0x18]; 3574 3575 u8 syndrome[0x20]; 3576 3577 u8 reserved_1[0x40]; 3578 }; 3579 3580 struct mlx5_ifc_set_issi_in_bits { 3581 u8 opcode[0x10]; 3582 u8 reserved_0[0x10]; 3583 3584 u8 reserved_1[0x10]; 3585 u8 op_mod[0x10]; 3586 3587 u8 reserved_2[0x10]; 3588 u8 current_issi[0x10]; 3589 3590 u8 reserved_3[0x20]; 3591 }; 3592 3593 struct mlx5_ifc_set_hca_cap_out_bits { 3594 u8 status[0x8]; 3595 u8 reserved_0[0x18]; 3596 3597 u8 syndrome[0x20]; 3598 3599 u8 reserved_1[0x40]; 3600 }; 3601 3602 struct mlx5_ifc_set_hca_cap_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_0[0x10]; 3605 3606 u8 reserved_1[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 reserved_2[0x40]; 3610 3611 union mlx5_ifc_hca_cap_union_bits capability; 3612 }; 3613 3614 enum { 3615 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3616 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3617 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3618 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3619 }; 3620 3621 struct mlx5_ifc_set_flow_table_root_out_bits { 3622 u8 status[0x8]; 3623 u8 reserved_0[0x18]; 3624 3625 u8 syndrome[0x20]; 3626 3627 u8 reserved_1[0x40]; 3628 }; 3629 3630 struct mlx5_ifc_set_flow_table_root_in_bits { 3631 u8 opcode[0x10]; 3632 u8 reserved_0[0x10]; 3633 3634 u8 reserved_1[0x10]; 3635 u8 op_mod[0x10]; 3636 3637 u8 other_vport[0x1]; 3638 u8 reserved_2[0xf]; 3639 u8 vport_number[0x10]; 3640 3641 u8 reserved_3[0x20]; 3642 3643 u8 table_type[0x8]; 3644 u8 reserved_4[0x18]; 3645 3646 u8 reserved_5[0x8]; 3647 u8 table_id[0x18]; 3648 3649 u8 reserved_6[0x8]; 3650 u8 underlay_qpn[0x18]; 3651 3652 u8 reserved_7[0x120]; 3653 }; 3654 3655 struct mlx5_ifc_set_fte_out_bits { 3656 u8 status[0x8]; 3657 u8 reserved_0[0x18]; 3658 3659 u8 syndrome[0x20]; 3660 3661 u8 reserved_1[0x40]; 3662 }; 3663 3664 struct mlx5_ifc_set_fte_in_bits { 3665 u8 opcode[0x10]; 3666 u8 reserved_0[0x10]; 3667 3668 u8 reserved_1[0x10]; 3669 u8 op_mod[0x10]; 3670 3671 u8 other_vport[0x1]; 3672 u8 reserved_2[0xf]; 3673 u8 vport_number[0x10]; 3674 3675 u8 reserved_3[0x20]; 3676 3677 u8 table_type[0x8]; 3678 u8 reserved_4[0x18]; 3679 3680 u8 reserved_5[0x8]; 3681 u8 table_id[0x18]; 3682 3683 u8 reserved_6[0x18]; 3684 u8 modify_enable_mask[0x8]; 3685 3686 u8 reserved_7[0x20]; 3687 3688 u8 flow_index[0x20]; 3689 3690 u8 reserved_8[0xe0]; 3691 3692 struct mlx5_ifc_flow_context_bits flow_context; 3693 }; 3694 3695 struct mlx5_ifc_set_driver_version_out_bits { 3696 u8 status[0x8]; 3697 u8 reserved_0[0x18]; 3698 3699 u8 syndrome[0x20]; 3700 3701 u8 reserved_1[0x40]; 3702 }; 3703 3704 struct mlx5_ifc_set_driver_version_in_bits { 3705 u8 opcode[0x10]; 3706 u8 reserved_0[0x10]; 3707 3708 u8 reserved_1[0x10]; 3709 u8 op_mod[0x10]; 3710 3711 u8 reserved_2[0x40]; 3712 3713 u8 driver_version[64][0x8]; 3714 }; 3715 3716 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3717 u8 status[0x8]; 3718 u8 reserved_0[0x18]; 3719 3720 u8 syndrome[0x20]; 3721 3722 u8 reserved_1[0x40]; 3723 }; 3724 3725 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3726 u8 opcode[0x10]; 3727 u8 reserved_0[0x10]; 3728 3729 u8 reserved_1[0x10]; 3730 u8 op_mod[0x10]; 3731 3732 u8 enable[0x1]; 3733 u8 reserved_2[0x1f]; 3734 3735 u8 reserved_3[0x160]; 3736 3737 struct mlx5_ifc_cmd_pas_bits pas; 3738 }; 3739 3740 struct mlx5_ifc_set_burst_size_out_bits { 3741 u8 status[0x8]; 3742 u8 reserved_0[0x18]; 3743 3744 u8 syndrome[0x20]; 3745 3746 u8 reserved_1[0x40]; 3747 }; 3748 3749 struct mlx5_ifc_set_burst_size_in_bits { 3750 u8 opcode[0x10]; 3751 u8 reserved_0[0x10]; 3752 3753 u8 reserved_1[0x10]; 3754 u8 op_mod[0x10]; 3755 3756 u8 reserved_2[0x20]; 3757 3758 u8 reserved_3[0x9]; 3759 u8 device_burst_size[0x17]; 3760 }; 3761 3762 struct mlx5_ifc_rts2rts_qp_out_bits { 3763 u8 status[0x8]; 3764 u8 reserved_0[0x18]; 3765 3766 u8 syndrome[0x20]; 3767 3768 u8 reserved_1[0x40]; 3769 }; 3770 3771 struct mlx5_ifc_rts2rts_qp_in_bits { 3772 u8 opcode[0x10]; 3773 u8 reserved_0[0x10]; 3774 3775 u8 reserved_1[0x10]; 3776 u8 op_mod[0x10]; 3777 3778 u8 reserved_2[0x8]; 3779 u8 qpn[0x18]; 3780 3781 u8 reserved_3[0x20]; 3782 3783 u8 opt_param_mask[0x20]; 3784 3785 u8 reserved_4[0x20]; 3786 3787 struct mlx5_ifc_qpc_bits qpc; 3788 3789 u8 reserved_5[0x80]; 3790 }; 3791 3792 struct mlx5_ifc_rtr2rts_qp_out_bits { 3793 u8 status[0x8]; 3794 u8 reserved_0[0x18]; 3795 3796 u8 syndrome[0x20]; 3797 3798 u8 reserved_1[0x40]; 3799 }; 3800 3801 struct mlx5_ifc_rtr2rts_qp_in_bits { 3802 u8 opcode[0x10]; 3803 u8 reserved_0[0x10]; 3804 3805 u8 reserved_1[0x10]; 3806 u8 op_mod[0x10]; 3807 3808 u8 reserved_2[0x8]; 3809 u8 qpn[0x18]; 3810 3811 u8 reserved_3[0x20]; 3812 3813 u8 opt_param_mask[0x20]; 3814 3815 u8 reserved_4[0x20]; 3816 3817 struct mlx5_ifc_qpc_bits qpc; 3818 3819 u8 reserved_5[0x80]; 3820 }; 3821 3822 struct mlx5_ifc_rst2init_qp_out_bits { 3823 u8 status[0x8]; 3824 u8 reserved_0[0x18]; 3825 3826 u8 syndrome[0x20]; 3827 3828 u8 reserved_1[0x40]; 3829 }; 3830 3831 struct mlx5_ifc_rst2init_qp_in_bits { 3832 u8 opcode[0x10]; 3833 u8 reserved_0[0x10]; 3834 3835 u8 reserved_1[0x10]; 3836 u8 op_mod[0x10]; 3837 3838 u8 reserved_2[0x8]; 3839 u8 qpn[0x18]; 3840 3841 u8 reserved_3[0x20]; 3842 3843 u8 opt_param_mask[0x20]; 3844 3845 u8 reserved_4[0x20]; 3846 3847 struct mlx5_ifc_qpc_bits qpc; 3848 3849 u8 reserved_5[0x80]; 3850 }; 3851 3852 struct mlx5_ifc_resume_qp_out_bits { 3853 u8 status[0x8]; 3854 u8 reserved_0[0x18]; 3855 3856 u8 syndrome[0x20]; 3857 3858 u8 reserved_1[0x40]; 3859 }; 3860 3861 struct mlx5_ifc_resume_qp_in_bits { 3862 u8 opcode[0x10]; 3863 u8 reserved_0[0x10]; 3864 3865 u8 reserved_1[0x10]; 3866 u8 op_mod[0x10]; 3867 3868 u8 reserved_2[0x8]; 3869 u8 qpn[0x18]; 3870 3871 u8 reserved_3[0x20]; 3872 }; 3873 3874 struct mlx5_ifc_query_xrc_srq_out_bits { 3875 u8 status[0x8]; 3876 u8 reserved_0[0x18]; 3877 3878 u8 syndrome[0x20]; 3879 3880 u8 reserved_1[0x40]; 3881 3882 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3883 3884 u8 reserved_2[0x600]; 3885 3886 u8 pas[0][0x40]; 3887 }; 3888 3889 struct mlx5_ifc_query_xrc_srq_in_bits { 3890 u8 opcode[0x10]; 3891 u8 reserved_0[0x10]; 3892 3893 u8 reserved_1[0x10]; 3894 u8 op_mod[0x10]; 3895 3896 u8 reserved_2[0x8]; 3897 u8 xrc_srqn[0x18]; 3898 3899 u8 reserved_3[0x20]; 3900 }; 3901 3902 struct mlx5_ifc_query_wol_rol_out_bits { 3903 u8 status[0x8]; 3904 u8 reserved_0[0x18]; 3905 3906 u8 syndrome[0x20]; 3907 3908 u8 reserved_1[0x10]; 3909 u8 rol_mode[0x8]; 3910 u8 wol_mode[0x8]; 3911 3912 u8 reserved_2[0x20]; 3913 }; 3914 3915 struct mlx5_ifc_query_wol_rol_in_bits { 3916 u8 opcode[0x10]; 3917 u8 reserved_0[0x10]; 3918 3919 u8 reserved_1[0x10]; 3920 u8 op_mod[0x10]; 3921 3922 u8 reserved_2[0x40]; 3923 }; 3924 3925 enum { 3926 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3927 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3928 }; 3929 3930 struct mlx5_ifc_query_vport_state_out_bits { 3931 u8 status[0x8]; 3932 u8 reserved_0[0x18]; 3933 3934 u8 syndrome[0x20]; 3935 3936 u8 reserved_1[0x20]; 3937 3938 u8 reserved_2[0x18]; 3939 u8 admin_state[0x4]; 3940 u8 state[0x4]; 3941 }; 3942 3943 enum { 3944 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3945 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3946 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3947 }; 3948 3949 struct mlx5_ifc_query_vport_state_in_bits { 3950 u8 opcode[0x10]; 3951 u8 reserved_0[0x10]; 3952 3953 u8 reserved_1[0x10]; 3954 u8 op_mod[0x10]; 3955 3956 u8 other_vport[0x1]; 3957 u8 reserved_2[0xf]; 3958 u8 vport_number[0x10]; 3959 3960 u8 reserved_3[0x20]; 3961 }; 3962 3963 struct mlx5_ifc_query_vnic_env_out_bits { 3964 u8 status[0x8]; 3965 u8 reserved_at_8[0x18]; 3966 3967 u8 syndrome[0x20]; 3968 3969 u8 reserved_at_40[0x40]; 3970 3971 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3972 }; 3973 3974 enum { 3975 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3976 }; 3977 3978 struct mlx5_ifc_query_vnic_env_in_bits { 3979 u8 opcode[0x10]; 3980 u8 reserved_at_10[0x10]; 3981 3982 u8 reserved_at_20[0x10]; 3983 u8 op_mod[0x10]; 3984 3985 u8 other_vport[0x1]; 3986 u8 reserved_at_41[0xf]; 3987 u8 vport_number[0x10]; 3988 3989 u8 reserved_at_60[0x20]; 3990 }; 3991 3992 struct mlx5_ifc_query_vport_counter_out_bits { 3993 u8 status[0x8]; 3994 u8 reserved_0[0x18]; 3995 3996 u8 syndrome[0x20]; 3997 3998 u8 reserved_1[0x40]; 3999 4000 struct mlx5_ifc_traffic_counter_bits received_errors; 4001 4002 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4003 4004 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4005 4006 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4007 4008 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4009 4010 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4011 4012 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4013 4014 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4015 4016 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4017 4018 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4019 4020 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4021 4022 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4023 4024 u8 reserved_2[0xa00]; 4025 }; 4026 4027 enum { 4028 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4029 }; 4030 4031 struct mlx5_ifc_query_vport_counter_in_bits { 4032 u8 opcode[0x10]; 4033 u8 reserved_0[0x10]; 4034 4035 u8 reserved_1[0x10]; 4036 u8 op_mod[0x10]; 4037 4038 u8 other_vport[0x1]; 4039 u8 reserved_2[0xb]; 4040 u8 port_num[0x4]; 4041 u8 vport_number[0x10]; 4042 4043 u8 reserved_3[0x60]; 4044 4045 u8 clear[0x1]; 4046 u8 reserved_4[0x1f]; 4047 4048 u8 reserved_5[0x20]; 4049 }; 4050 4051 struct mlx5_ifc_query_tis_out_bits { 4052 u8 status[0x8]; 4053 u8 reserved_0[0x18]; 4054 4055 u8 syndrome[0x20]; 4056 4057 u8 reserved_1[0x40]; 4058 4059 struct mlx5_ifc_tisc_bits tis_context; 4060 }; 4061 4062 struct mlx5_ifc_query_tis_in_bits { 4063 u8 opcode[0x10]; 4064 u8 reserved_0[0x10]; 4065 4066 u8 reserved_1[0x10]; 4067 u8 op_mod[0x10]; 4068 4069 u8 reserved_2[0x8]; 4070 u8 tisn[0x18]; 4071 4072 u8 reserved_3[0x20]; 4073 }; 4074 4075 struct mlx5_ifc_query_tir_out_bits { 4076 u8 status[0x8]; 4077 u8 reserved_0[0x18]; 4078 4079 u8 syndrome[0x20]; 4080 4081 u8 reserved_1[0xc0]; 4082 4083 struct mlx5_ifc_tirc_bits tir_context; 4084 }; 4085 4086 struct mlx5_ifc_query_tir_in_bits { 4087 u8 opcode[0x10]; 4088 u8 reserved_0[0x10]; 4089 4090 u8 reserved_1[0x10]; 4091 u8 op_mod[0x10]; 4092 4093 u8 reserved_2[0x8]; 4094 u8 tirn[0x18]; 4095 4096 u8 reserved_3[0x20]; 4097 }; 4098 4099 struct mlx5_ifc_query_srq_out_bits { 4100 u8 status[0x8]; 4101 u8 reserved_0[0x18]; 4102 4103 u8 syndrome[0x20]; 4104 4105 u8 reserved_1[0x40]; 4106 4107 struct mlx5_ifc_srqc_bits srq_context_entry; 4108 4109 u8 reserved_2[0x600]; 4110 4111 u8 pas[0][0x40]; 4112 }; 4113 4114 struct mlx5_ifc_query_srq_in_bits { 4115 u8 opcode[0x10]; 4116 u8 reserved_0[0x10]; 4117 4118 u8 reserved_1[0x10]; 4119 u8 op_mod[0x10]; 4120 4121 u8 reserved_2[0x8]; 4122 u8 srqn[0x18]; 4123 4124 u8 reserved_3[0x20]; 4125 }; 4126 4127 struct mlx5_ifc_query_sq_out_bits { 4128 u8 status[0x8]; 4129 u8 reserved_0[0x18]; 4130 4131 u8 syndrome[0x20]; 4132 4133 u8 reserved_1[0xc0]; 4134 4135 struct mlx5_ifc_sqc_bits sq_context; 4136 }; 4137 4138 struct mlx5_ifc_query_sq_in_bits { 4139 u8 opcode[0x10]; 4140 u8 reserved_0[0x10]; 4141 4142 u8 reserved_1[0x10]; 4143 u8 op_mod[0x10]; 4144 4145 u8 reserved_2[0x8]; 4146 u8 sqn[0x18]; 4147 4148 u8 reserved_3[0x20]; 4149 }; 4150 4151 struct mlx5_ifc_query_special_contexts_out_bits { 4152 u8 status[0x8]; 4153 u8 reserved_0[0x18]; 4154 4155 u8 syndrome[0x20]; 4156 4157 u8 dump_fill_mkey[0x20]; 4158 4159 u8 resd_lkey[0x20]; 4160 }; 4161 4162 struct mlx5_ifc_query_special_contexts_in_bits { 4163 u8 opcode[0x10]; 4164 u8 reserved_0[0x10]; 4165 4166 u8 reserved_1[0x10]; 4167 u8 op_mod[0x10]; 4168 4169 u8 reserved_2[0x40]; 4170 }; 4171 4172 struct mlx5_ifc_query_scheduling_element_out_bits { 4173 u8 status[0x8]; 4174 u8 reserved_at_8[0x18]; 4175 4176 u8 syndrome[0x20]; 4177 4178 u8 reserved_at_40[0xc0]; 4179 4180 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4181 4182 u8 reserved_at_300[0x100]; 4183 }; 4184 4185 enum { 4186 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4187 }; 4188 4189 struct mlx5_ifc_query_scheduling_element_in_bits { 4190 u8 opcode[0x10]; 4191 u8 reserved_at_10[0x10]; 4192 4193 u8 reserved_at_20[0x10]; 4194 u8 op_mod[0x10]; 4195 4196 u8 scheduling_hierarchy[0x8]; 4197 u8 reserved_at_48[0x18]; 4198 4199 u8 scheduling_element_id[0x20]; 4200 4201 u8 reserved_at_80[0x180]; 4202 }; 4203 4204 struct mlx5_ifc_query_rqt_out_bits { 4205 u8 status[0x8]; 4206 u8 reserved_0[0x18]; 4207 4208 u8 syndrome[0x20]; 4209 4210 u8 reserved_1[0xc0]; 4211 4212 struct mlx5_ifc_rqtc_bits rqt_context; 4213 }; 4214 4215 struct mlx5_ifc_query_rqt_in_bits { 4216 u8 opcode[0x10]; 4217 u8 reserved_0[0x10]; 4218 4219 u8 reserved_1[0x10]; 4220 u8 op_mod[0x10]; 4221 4222 u8 reserved_2[0x8]; 4223 u8 rqtn[0x18]; 4224 4225 u8 reserved_3[0x20]; 4226 }; 4227 4228 struct mlx5_ifc_query_rq_out_bits { 4229 u8 status[0x8]; 4230 u8 reserved_0[0x18]; 4231 4232 u8 syndrome[0x20]; 4233 4234 u8 reserved_1[0xc0]; 4235 4236 struct mlx5_ifc_rqc_bits rq_context; 4237 }; 4238 4239 struct mlx5_ifc_query_rq_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_0[0x10]; 4242 4243 u8 reserved_1[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 reserved_2[0x8]; 4247 u8 rqn[0x18]; 4248 4249 u8 reserved_3[0x20]; 4250 }; 4251 4252 struct mlx5_ifc_query_roce_address_out_bits { 4253 u8 status[0x8]; 4254 u8 reserved_0[0x18]; 4255 4256 u8 syndrome[0x20]; 4257 4258 u8 reserved_1[0x40]; 4259 4260 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4261 }; 4262 4263 struct mlx5_ifc_query_roce_address_in_bits { 4264 u8 opcode[0x10]; 4265 u8 reserved_0[0x10]; 4266 4267 u8 reserved_1[0x10]; 4268 u8 op_mod[0x10]; 4269 4270 u8 roce_address_index[0x10]; 4271 u8 reserved_2[0x10]; 4272 4273 u8 reserved_3[0x20]; 4274 }; 4275 4276 struct mlx5_ifc_query_rmp_out_bits { 4277 u8 status[0x8]; 4278 u8 reserved_0[0x18]; 4279 4280 u8 syndrome[0x20]; 4281 4282 u8 reserved_1[0xc0]; 4283 4284 struct mlx5_ifc_rmpc_bits rmp_context; 4285 }; 4286 4287 struct mlx5_ifc_query_rmp_in_bits { 4288 u8 opcode[0x10]; 4289 u8 reserved_0[0x10]; 4290 4291 u8 reserved_1[0x10]; 4292 u8 op_mod[0x10]; 4293 4294 u8 reserved_2[0x8]; 4295 u8 rmpn[0x18]; 4296 4297 u8 reserved_3[0x20]; 4298 }; 4299 4300 struct mlx5_ifc_query_rdb_out_bits { 4301 u8 status[0x8]; 4302 u8 reserved_0[0x18]; 4303 4304 u8 syndrome[0x20]; 4305 4306 u8 reserved_1[0x20]; 4307 4308 u8 reserved_2[0x18]; 4309 u8 rdb_list_size[0x8]; 4310 4311 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4312 }; 4313 4314 struct mlx5_ifc_query_rdb_in_bits { 4315 u8 opcode[0x10]; 4316 u8 reserved_0[0x10]; 4317 4318 u8 reserved_1[0x10]; 4319 u8 op_mod[0x10]; 4320 4321 u8 reserved_2[0x8]; 4322 u8 qpn[0x18]; 4323 4324 u8 reserved_3[0x20]; 4325 }; 4326 4327 struct mlx5_ifc_query_qp_out_bits { 4328 u8 status[0x8]; 4329 u8 reserved_0[0x18]; 4330 4331 u8 syndrome[0x20]; 4332 4333 u8 reserved_1[0x40]; 4334 4335 u8 opt_param_mask[0x20]; 4336 4337 u8 reserved_2[0x20]; 4338 4339 struct mlx5_ifc_qpc_bits qpc; 4340 4341 u8 reserved_3[0x80]; 4342 4343 u8 pas[0][0x40]; 4344 }; 4345 4346 struct mlx5_ifc_query_qp_in_bits { 4347 u8 opcode[0x10]; 4348 u8 reserved_0[0x10]; 4349 4350 u8 reserved_1[0x10]; 4351 u8 op_mod[0x10]; 4352 4353 u8 reserved_2[0x8]; 4354 u8 qpn[0x18]; 4355 4356 u8 reserved_3[0x20]; 4357 }; 4358 4359 struct mlx5_ifc_query_q_counter_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_0[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_1[0x40]; 4366 4367 u8 rx_write_requests[0x20]; 4368 4369 u8 reserved_2[0x20]; 4370 4371 u8 rx_read_requests[0x20]; 4372 4373 u8 reserved_3[0x20]; 4374 4375 u8 rx_atomic_requests[0x20]; 4376 4377 u8 reserved_4[0x20]; 4378 4379 u8 rx_dct_connect[0x20]; 4380 4381 u8 reserved_5[0x20]; 4382 4383 u8 out_of_buffer[0x20]; 4384 4385 u8 reserved_7[0x20]; 4386 4387 u8 out_of_sequence[0x20]; 4388 4389 u8 reserved_8[0x20]; 4390 4391 u8 duplicate_request[0x20]; 4392 4393 u8 reserved_9[0x20]; 4394 4395 u8 rnr_nak_retry_err[0x20]; 4396 4397 u8 reserved_10[0x20]; 4398 4399 u8 packet_seq_err[0x20]; 4400 4401 u8 reserved_11[0x20]; 4402 4403 u8 implied_nak_seq_err[0x20]; 4404 4405 u8 reserved_12[0x20]; 4406 4407 u8 local_ack_timeout_err[0x20]; 4408 4409 u8 reserved_13[0x20]; 4410 4411 u8 resp_rnr_nak[0x20]; 4412 4413 u8 reserved_14[0x20]; 4414 4415 u8 req_rnr_retries_exceeded[0x20]; 4416 4417 u8 reserved_15[0x460]; 4418 }; 4419 4420 struct mlx5_ifc_query_q_counter_in_bits { 4421 u8 opcode[0x10]; 4422 u8 reserved_0[0x10]; 4423 4424 u8 reserved_1[0x10]; 4425 u8 op_mod[0x10]; 4426 4427 u8 reserved_2[0x80]; 4428 4429 u8 clear[0x1]; 4430 u8 reserved_3[0x1f]; 4431 4432 u8 reserved_4[0x18]; 4433 u8 counter_set_id[0x8]; 4434 }; 4435 4436 struct mlx5_ifc_query_pages_out_bits { 4437 u8 status[0x8]; 4438 u8 reserved_0[0x18]; 4439 4440 u8 syndrome[0x20]; 4441 4442 u8 reserved_1[0x10]; 4443 u8 function_id[0x10]; 4444 4445 u8 num_pages[0x20]; 4446 }; 4447 4448 enum { 4449 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4450 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4451 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4452 }; 4453 4454 struct mlx5_ifc_query_pages_in_bits { 4455 u8 opcode[0x10]; 4456 u8 reserved_0[0x10]; 4457 4458 u8 reserved_1[0x10]; 4459 u8 op_mod[0x10]; 4460 4461 u8 reserved_2[0x10]; 4462 u8 function_id[0x10]; 4463 4464 u8 reserved_3[0x20]; 4465 }; 4466 4467 struct mlx5_ifc_query_nic_vport_context_out_bits { 4468 u8 status[0x8]; 4469 u8 reserved_0[0x18]; 4470 4471 u8 syndrome[0x20]; 4472 4473 u8 reserved_1[0x40]; 4474 4475 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4476 }; 4477 4478 struct mlx5_ifc_query_nic_vport_context_in_bits { 4479 u8 opcode[0x10]; 4480 u8 reserved_0[0x10]; 4481 4482 u8 reserved_1[0x10]; 4483 u8 op_mod[0x10]; 4484 4485 u8 other_vport[0x1]; 4486 u8 reserved_2[0xf]; 4487 u8 vport_number[0x10]; 4488 4489 u8 reserved_3[0x5]; 4490 u8 allowed_list_type[0x3]; 4491 u8 reserved_4[0x18]; 4492 }; 4493 4494 struct mlx5_ifc_query_mkey_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_0[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 reserved_1[0x40]; 4501 4502 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4503 4504 u8 reserved_2[0x600]; 4505 4506 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4507 4508 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4509 }; 4510 4511 struct mlx5_ifc_query_mkey_in_bits { 4512 u8 opcode[0x10]; 4513 u8 reserved_0[0x10]; 4514 4515 u8 reserved_1[0x10]; 4516 u8 op_mod[0x10]; 4517 4518 u8 reserved_2[0x8]; 4519 u8 mkey_index[0x18]; 4520 4521 u8 pg_access[0x1]; 4522 u8 reserved_3[0x1f]; 4523 }; 4524 4525 struct mlx5_ifc_query_mad_demux_out_bits { 4526 u8 status[0x8]; 4527 u8 reserved_0[0x18]; 4528 4529 u8 syndrome[0x20]; 4530 4531 u8 reserved_1[0x40]; 4532 4533 u8 mad_dumux_parameters_block[0x20]; 4534 }; 4535 4536 struct mlx5_ifc_query_mad_demux_in_bits { 4537 u8 opcode[0x10]; 4538 u8 reserved_0[0x10]; 4539 4540 u8 reserved_1[0x10]; 4541 u8 op_mod[0x10]; 4542 4543 u8 reserved_2[0x40]; 4544 }; 4545 4546 struct mlx5_ifc_query_l2_table_entry_out_bits { 4547 u8 status[0x8]; 4548 u8 reserved_0[0x18]; 4549 4550 u8 syndrome[0x20]; 4551 4552 u8 reserved_1[0xa0]; 4553 4554 u8 reserved_2[0x13]; 4555 u8 vlan_valid[0x1]; 4556 u8 vlan[0xc]; 4557 4558 struct mlx5_ifc_mac_address_layout_bits mac_address; 4559 4560 u8 reserved_3[0xc0]; 4561 }; 4562 4563 struct mlx5_ifc_query_l2_table_entry_in_bits { 4564 u8 opcode[0x10]; 4565 u8 reserved_0[0x10]; 4566 4567 u8 reserved_1[0x10]; 4568 u8 op_mod[0x10]; 4569 4570 u8 reserved_2[0x60]; 4571 4572 u8 reserved_3[0x8]; 4573 u8 table_index[0x18]; 4574 4575 u8 reserved_4[0x140]; 4576 }; 4577 4578 struct mlx5_ifc_query_issi_out_bits { 4579 u8 status[0x8]; 4580 u8 reserved_0[0x18]; 4581 4582 u8 syndrome[0x20]; 4583 4584 u8 reserved_1[0x10]; 4585 u8 current_issi[0x10]; 4586 4587 u8 reserved_2[0xa0]; 4588 4589 u8 supported_issi_reserved[76][0x8]; 4590 u8 supported_issi_dw0[0x20]; 4591 }; 4592 4593 struct mlx5_ifc_query_issi_in_bits { 4594 u8 opcode[0x10]; 4595 u8 reserved_0[0x10]; 4596 4597 u8 reserved_1[0x10]; 4598 u8 op_mod[0x10]; 4599 4600 u8 reserved_2[0x40]; 4601 }; 4602 4603 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4604 u8 status[0x8]; 4605 u8 reserved_0[0x18]; 4606 4607 u8 syndrome[0x20]; 4608 4609 u8 reserved_1[0x40]; 4610 4611 struct mlx5_ifc_pkey_bits pkey[0]; 4612 }; 4613 4614 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4615 u8 opcode[0x10]; 4616 u8 reserved_0[0x10]; 4617 4618 u8 reserved_1[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 other_vport[0x1]; 4622 u8 reserved_2[0xb]; 4623 u8 port_num[0x4]; 4624 u8 vport_number[0x10]; 4625 4626 u8 reserved_3[0x10]; 4627 u8 pkey_index[0x10]; 4628 }; 4629 4630 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_0[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_1[0x20]; 4637 4638 u8 gids_num[0x10]; 4639 u8 reserved_2[0x10]; 4640 4641 struct mlx5_ifc_array128_auto_bits gid[0]; 4642 }; 4643 4644 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4645 u8 opcode[0x10]; 4646 u8 reserved_0[0x10]; 4647 4648 u8 reserved_1[0x10]; 4649 u8 op_mod[0x10]; 4650 4651 u8 other_vport[0x1]; 4652 u8 reserved_2[0xb]; 4653 u8 port_num[0x4]; 4654 u8 vport_number[0x10]; 4655 4656 u8 reserved_3[0x10]; 4657 u8 gid_index[0x10]; 4658 }; 4659 4660 struct mlx5_ifc_query_hca_vport_context_out_bits { 4661 u8 status[0x8]; 4662 u8 reserved_0[0x18]; 4663 4664 u8 syndrome[0x20]; 4665 4666 u8 reserved_1[0x40]; 4667 4668 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4669 }; 4670 4671 struct mlx5_ifc_query_hca_vport_context_in_bits { 4672 u8 opcode[0x10]; 4673 u8 reserved_0[0x10]; 4674 4675 u8 reserved_1[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 other_vport[0x1]; 4679 u8 reserved_2[0xb]; 4680 u8 port_num[0x4]; 4681 u8 vport_number[0x10]; 4682 4683 u8 reserved_3[0x20]; 4684 }; 4685 4686 struct mlx5_ifc_query_hca_cap_out_bits { 4687 u8 status[0x8]; 4688 u8 reserved_0[0x18]; 4689 4690 u8 syndrome[0x20]; 4691 4692 u8 reserved_1[0x40]; 4693 4694 union mlx5_ifc_hca_cap_union_bits capability; 4695 }; 4696 4697 struct mlx5_ifc_query_hca_cap_in_bits { 4698 u8 opcode[0x10]; 4699 u8 reserved_0[0x10]; 4700 4701 u8 reserved_1[0x10]; 4702 u8 op_mod[0x10]; 4703 4704 u8 reserved_2[0x40]; 4705 }; 4706 4707 struct mlx5_ifc_query_flow_table_out_bits { 4708 u8 status[0x8]; 4709 u8 reserved_at_8[0x18]; 4710 4711 u8 syndrome[0x20]; 4712 4713 u8 reserved_at_40[0x80]; 4714 4715 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4716 }; 4717 4718 struct mlx5_ifc_query_flow_table_in_bits { 4719 u8 opcode[0x10]; 4720 u8 reserved_0[0x10]; 4721 4722 u8 reserved_1[0x10]; 4723 u8 op_mod[0x10]; 4724 4725 u8 other_vport[0x1]; 4726 u8 reserved_2[0xf]; 4727 u8 vport_number[0x10]; 4728 4729 u8 reserved_3[0x20]; 4730 4731 u8 table_type[0x8]; 4732 u8 reserved_4[0x18]; 4733 4734 u8 reserved_5[0x8]; 4735 u8 table_id[0x18]; 4736 4737 u8 reserved_6[0x140]; 4738 }; 4739 4740 struct mlx5_ifc_query_fte_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_0[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_1[0x1c0]; 4747 4748 struct mlx5_ifc_flow_context_bits flow_context; 4749 }; 4750 4751 struct mlx5_ifc_query_fte_in_bits { 4752 u8 opcode[0x10]; 4753 u8 reserved_0[0x10]; 4754 4755 u8 reserved_1[0x10]; 4756 u8 op_mod[0x10]; 4757 4758 u8 other_vport[0x1]; 4759 u8 reserved_2[0xf]; 4760 u8 vport_number[0x10]; 4761 4762 u8 reserved_3[0x20]; 4763 4764 u8 table_type[0x8]; 4765 u8 reserved_4[0x18]; 4766 4767 u8 reserved_5[0x8]; 4768 u8 table_id[0x18]; 4769 4770 u8 reserved_6[0x40]; 4771 4772 u8 flow_index[0x20]; 4773 4774 u8 reserved_7[0xe0]; 4775 }; 4776 4777 enum { 4778 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4779 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4780 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4781 }; 4782 4783 struct mlx5_ifc_query_flow_group_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_0[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_1[0xa0]; 4790 4791 u8 start_flow_index[0x20]; 4792 4793 u8 reserved_2[0x20]; 4794 4795 u8 end_flow_index[0x20]; 4796 4797 u8 reserved_3[0xa0]; 4798 4799 u8 reserved_4[0x18]; 4800 u8 match_criteria_enable[0x8]; 4801 4802 struct mlx5_ifc_fte_match_param_bits match_criteria; 4803 4804 u8 reserved_5[0xe00]; 4805 }; 4806 4807 struct mlx5_ifc_query_flow_group_in_bits { 4808 u8 opcode[0x10]; 4809 u8 reserved_0[0x10]; 4810 4811 u8 reserved_1[0x10]; 4812 u8 op_mod[0x10]; 4813 4814 u8 other_vport[0x1]; 4815 u8 reserved_2[0xf]; 4816 u8 vport_number[0x10]; 4817 4818 u8 reserved_3[0x20]; 4819 4820 u8 table_type[0x8]; 4821 u8 reserved_4[0x18]; 4822 4823 u8 reserved_5[0x8]; 4824 u8 table_id[0x18]; 4825 4826 u8 group_id[0x20]; 4827 4828 u8 reserved_6[0x120]; 4829 }; 4830 4831 struct mlx5_ifc_query_flow_counter_out_bits { 4832 u8 status[0x8]; 4833 u8 reserved_at_8[0x18]; 4834 4835 u8 syndrome[0x20]; 4836 4837 u8 reserved_at_40[0x40]; 4838 4839 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4840 }; 4841 4842 struct mlx5_ifc_query_flow_counter_in_bits { 4843 u8 opcode[0x10]; 4844 u8 reserved_at_10[0x10]; 4845 4846 u8 reserved_at_20[0x10]; 4847 u8 op_mod[0x10]; 4848 4849 u8 reserved_at_40[0x80]; 4850 4851 u8 clear[0x1]; 4852 u8 reserved_at_c1[0xf]; 4853 u8 num_of_counters[0x10]; 4854 4855 u8 reserved_at_e0[0x10]; 4856 u8 flow_counter_id[0x10]; 4857 }; 4858 4859 struct mlx5_ifc_query_esw_vport_context_out_bits { 4860 u8 status[0x8]; 4861 u8 reserved_0[0x18]; 4862 4863 u8 syndrome[0x20]; 4864 4865 u8 reserved_1[0x40]; 4866 4867 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4868 }; 4869 4870 struct mlx5_ifc_query_esw_vport_context_in_bits { 4871 u8 opcode[0x10]; 4872 u8 reserved_0[0x10]; 4873 4874 u8 reserved_1[0x10]; 4875 u8 op_mod[0x10]; 4876 4877 u8 other_vport[0x1]; 4878 u8 reserved_2[0xf]; 4879 u8 vport_number[0x10]; 4880 4881 u8 reserved_3[0x20]; 4882 }; 4883 4884 struct mlx5_ifc_query_eq_out_bits { 4885 u8 status[0x8]; 4886 u8 reserved_0[0x18]; 4887 4888 u8 syndrome[0x20]; 4889 4890 u8 reserved_1[0x40]; 4891 4892 struct mlx5_ifc_eqc_bits eq_context_entry; 4893 4894 u8 reserved_2[0x40]; 4895 4896 u8 event_bitmask[0x40]; 4897 4898 u8 reserved_3[0x580]; 4899 4900 u8 pas[0][0x40]; 4901 }; 4902 4903 struct mlx5_ifc_query_eq_in_bits { 4904 u8 opcode[0x10]; 4905 u8 reserved_0[0x10]; 4906 4907 u8 reserved_1[0x10]; 4908 u8 op_mod[0x10]; 4909 4910 u8 reserved_2[0x18]; 4911 u8 eq_number[0x8]; 4912 4913 u8 reserved_3[0x20]; 4914 }; 4915 4916 struct mlx5_ifc_query_dct_out_bits { 4917 u8 status[0x8]; 4918 u8 reserved_0[0x18]; 4919 4920 u8 syndrome[0x20]; 4921 4922 u8 reserved_1[0x40]; 4923 4924 struct mlx5_ifc_dctc_bits dct_context_entry; 4925 4926 u8 reserved_2[0x180]; 4927 }; 4928 4929 struct mlx5_ifc_query_dct_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_0[0x10]; 4932 4933 u8 reserved_1[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_2[0x8]; 4937 u8 dctn[0x18]; 4938 4939 u8 reserved_3[0x20]; 4940 }; 4941 4942 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_0[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 enable[0x1]; 4949 u8 reserved_1[0x1f]; 4950 4951 u8 reserved_2[0x160]; 4952 4953 struct mlx5_ifc_cmd_pas_bits pas; 4954 }; 4955 4956 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_0[0x10]; 4959 4960 u8 reserved_1[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_2[0x40]; 4964 }; 4965 4966 struct mlx5_ifc_query_cq_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_0[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_1[0x40]; 4973 4974 struct mlx5_ifc_cqc_bits cq_context; 4975 4976 u8 reserved_2[0x600]; 4977 4978 u8 pas[0][0x40]; 4979 }; 4980 4981 struct mlx5_ifc_query_cq_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_0[0x10]; 4984 4985 u8 reserved_1[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 reserved_2[0x8]; 4989 u8 cqn[0x18]; 4990 4991 u8 reserved_3[0x20]; 4992 }; 4993 4994 struct mlx5_ifc_query_cong_status_out_bits { 4995 u8 status[0x8]; 4996 u8 reserved_0[0x18]; 4997 4998 u8 syndrome[0x20]; 4999 5000 u8 reserved_1[0x20]; 5001 5002 u8 enable[0x1]; 5003 u8 tag_enable[0x1]; 5004 u8 reserved_2[0x1e]; 5005 }; 5006 5007 struct mlx5_ifc_query_cong_status_in_bits { 5008 u8 opcode[0x10]; 5009 u8 reserved_0[0x10]; 5010 5011 u8 reserved_1[0x10]; 5012 u8 op_mod[0x10]; 5013 5014 u8 reserved_2[0x18]; 5015 u8 priority[0x4]; 5016 u8 cong_protocol[0x4]; 5017 5018 u8 reserved_3[0x20]; 5019 }; 5020 5021 struct mlx5_ifc_query_cong_statistics_out_bits { 5022 u8 status[0x8]; 5023 u8 reserved_0[0x18]; 5024 5025 u8 syndrome[0x20]; 5026 5027 u8 reserved_1[0x40]; 5028 5029 u8 rp_cur_flows[0x20]; 5030 5031 u8 sum_flows[0x20]; 5032 5033 u8 rp_cnp_ignored_high[0x20]; 5034 5035 u8 rp_cnp_ignored_low[0x20]; 5036 5037 u8 rp_cnp_handled_high[0x20]; 5038 5039 u8 rp_cnp_handled_low[0x20]; 5040 5041 u8 reserved_2[0x100]; 5042 5043 u8 time_stamp_high[0x20]; 5044 5045 u8 time_stamp_low[0x20]; 5046 5047 u8 accumulators_period[0x20]; 5048 5049 u8 np_ecn_marked_roce_packets_high[0x20]; 5050 5051 u8 np_ecn_marked_roce_packets_low[0x20]; 5052 5053 u8 np_cnp_sent_high[0x20]; 5054 5055 u8 np_cnp_sent_low[0x20]; 5056 5057 u8 reserved_3[0x560]; 5058 }; 5059 5060 struct mlx5_ifc_query_cong_statistics_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_0[0x10]; 5063 5064 u8 reserved_1[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 clear[0x1]; 5068 u8 reserved_2[0x1f]; 5069 5070 u8 reserved_3[0x20]; 5071 }; 5072 5073 struct mlx5_ifc_query_cong_params_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_0[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_1[0x40]; 5080 5081 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5082 }; 5083 5084 struct mlx5_ifc_query_cong_params_in_bits { 5085 u8 opcode[0x10]; 5086 u8 reserved_0[0x10]; 5087 5088 u8 reserved_1[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_2[0x1c]; 5092 u8 cong_protocol[0x4]; 5093 5094 u8 reserved_3[0x20]; 5095 }; 5096 5097 struct mlx5_ifc_query_burst_size_out_bits { 5098 u8 status[0x8]; 5099 u8 reserved_0[0x18]; 5100 5101 u8 syndrome[0x20]; 5102 5103 u8 reserved_1[0x20]; 5104 5105 u8 reserved_2[0x9]; 5106 u8 device_burst_size[0x17]; 5107 }; 5108 5109 struct mlx5_ifc_query_burst_size_in_bits { 5110 u8 opcode[0x10]; 5111 u8 reserved_0[0x10]; 5112 5113 u8 reserved_1[0x10]; 5114 u8 op_mod[0x10]; 5115 5116 u8 reserved_2[0x40]; 5117 }; 5118 5119 struct mlx5_ifc_query_adapter_out_bits { 5120 u8 status[0x8]; 5121 u8 reserved_0[0x18]; 5122 5123 u8 syndrome[0x20]; 5124 5125 u8 reserved_1[0x40]; 5126 5127 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5128 }; 5129 5130 struct mlx5_ifc_query_adapter_in_bits { 5131 u8 opcode[0x10]; 5132 u8 reserved_0[0x10]; 5133 5134 u8 reserved_1[0x10]; 5135 u8 op_mod[0x10]; 5136 5137 u8 reserved_2[0x40]; 5138 }; 5139 5140 struct mlx5_ifc_qp_2rst_out_bits { 5141 u8 status[0x8]; 5142 u8 reserved_0[0x18]; 5143 5144 u8 syndrome[0x20]; 5145 5146 u8 reserved_1[0x40]; 5147 }; 5148 5149 struct mlx5_ifc_qp_2rst_in_bits { 5150 u8 opcode[0x10]; 5151 u8 reserved_0[0x10]; 5152 5153 u8 reserved_1[0x10]; 5154 u8 op_mod[0x10]; 5155 5156 u8 reserved_2[0x8]; 5157 u8 qpn[0x18]; 5158 5159 u8 reserved_3[0x20]; 5160 }; 5161 5162 struct mlx5_ifc_qp_2err_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_0[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_1[0x40]; 5169 }; 5170 5171 struct mlx5_ifc_qp_2err_in_bits { 5172 u8 opcode[0x10]; 5173 u8 reserved_0[0x10]; 5174 5175 u8 reserved_1[0x10]; 5176 u8 op_mod[0x10]; 5177 5178 u8 reserved_2[0x8]; 5179 u8 qpn[0x18]; 5180 5181 u8 reserved_3[0x20]; 5182 }; 5183 5184 struct mlx5_ifc_para_vport_element_bits { 5185 u8 reserved_at_0[0xc]; 5186 u8 traffic_class[0x4]; 5187 u8 qos_para_vport_number[0x10]; 5188 }; 5189 5190 struct mlx5_ifc_page_fault_resume_out_bits { 5191 u8 status[0x8]; 5192 u8 reserved_0[0x18]; 5193 5194 u8 syndrome[0x20]; 5195 5196 u8 reserved_1[0x40]; 5197 }; 5198 5199 struct mlx5_ifc_page_fault_resume_in_bits { 5200 u8 opcode[0x10]; 5201 u8 reserved_0[0x10]; 5202 5203 u8 reserved_1[0x10]; 5204 u8 op_mod[0x10]; 5205 5206 u8 error[0x1]; 5207 u8 reserved_2[0x4]; 5208 u8 rdma[0x1]; 5209 u8 read_write[0x1]; 5210 u8 req_res[0x1]; 5211 u8 qpn[0x18]; 5212 5213 u8 reserved_3[0x20]; 5214 }; 5215 5216 struct mlx5_ifc_nop_out_bits { 5217 u8 status[0x8]; 5218 u8 reserved_0[0x18]; 5219 5220 u8 syndrome[0x20]; 5221 5222 u8 reserved_1[0x40]; 5223 }; 5224 5225 struct mlx5_ifc_nop_in_bits { 5226 u8 opcode[0x10]; 5227 u8 reserved_0[0x10]; 5228 5229 u8 reserved_1[0x10]; 5230 u8 op_mod[0x10]; 5231 5232 u8 reserved_2[0x40]; 5233 }; 5234 5235 struct mlx5_ifc_modify_vport_state_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_0[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_1[0x40]; 5242 }; 5243 5244 enum { 5245 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5246 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5247 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5248 }; 5249 5250 enum { 5251 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5252 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5253 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5254 }; 5255 5256 struct mlx5_ifc_modify_vport_state_in_bits { 5257 u8 opcode[0x10]; 5258 u8 reserved_0[0x10]; 5259 5260 u8 reserved_1[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 other_vport[0x1]; 5264 u8 reserved_2[0xf]; 5265 u8 vport_number[0x10]; 5266 5267 u8 reserved_3[0x18]; 5268 u8 admin_state[0x4]; 5269 u8 reserved_4[0x4]; 5270 }; 5271 5272 struct mlx5_ifc_modify_tis_out_bits { 5273 u8 status[0x8]; 5274 u8 reserved_0[0x18]; 5275 5276 u8 syndrome[0x20]; 5277 5278 u8 reserved_1[0x40]; 5279 }; 5280 5281 struct mlx5_ifc_modify_tis_bitmask_bits { 5282 u8 reserved_at_0[0x20]; 5283 5284 u8 reserved_at_20[0x1d]; 5285 u8 lag_tx_port_affinity[0x1]; 5286 u8 strict_lag_tx_port_affinity[0x1]; 5287 u8 prio[0x1]; 5288 }; 5289 5290 struct mlx5_ifc_modify_tis_in_bits { 5291 u8 opcode[0x10]; 5292 u8 reserved_0[0x10]; 5293 5294 u8 reserved_1[0x10]; 5295 u8 op_mod[0x10]; 5296 5297 u8 reserved_2[0x8]; 5298 u8 tisn[0x18]; 5299 5300 u8 reserved_3[0x20]; 5301 5302 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5303 5304 u8 reserved_4[0x40]; 5305 5306 struct mlx5_ifc_tisc_bits ctx; 5307 }; 5308 5309 struct mlx5_ifc_modify_tir_out_bits { 5310 u8 status[0x8]; 5311 u8 reserved_0[0x18]; 5312 5313 u8 syndrome[0x20]; 5314 5315 u8 reserved_1[0x40]; 5316 }; 5317 5318 enum 5319 { 5320 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5321 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5322 }; 5323 5324 struct mlx5_ifc_modify_tir_in_bits { 5325 u8 opcode[0x10]; 5326 u8 reserved_0[0x10]; 5327 5328 u8 reserved_1[0x10]; 5329 u8 op_mod[0x10]; 5330 5331 u8 reserved_2[0x8]; 5332 u8 tirn[0x18]; 5333 5334 u8 reserved_3[0x20]; 5335 5336 u8 modify_bitmask[0x40]; 5337 5338 u8 reserved_4[0x40]; 5339 5340 struct mlx5_ifc_tirc_bits tir_context; 5341 }; 5342 5343 struct mlx5_ifc_modify_sq_out_bits { 5344 u8 status[0x8]; 5345 u8 reserved_0[0x18]; 5346 5347 u8 syndrome[0x20]; 5348 5349 u8 reserved_1[0x40]; 5350 }; 5351 5352 struct mlx5_ifc_modify_sq_in_bits { 5353 u8 opcode[0x10]; 5354 u8 reserved_0[0x10]; 5355 5356 u8 reserved_1[0x10]; 5357 u8 op_mod[0x10]; 5358 5359 u8 sq_state[0x4]; 5360 u8 reserved_2[0x4]; 5361 u8 sqn[0x18]; 5362 5363 u8 reserved_3[0x20]; 5364 5365 u8 modify_bitmask[0x40]; 5366 5367 u8 reserved_4[0x40]; 5368 5369 struct mlx5_ifc_sqc_bits ctx; 5370 }; 5371 5372 struct mlx5_ifc_modify_scheduling_element_out_bits { 5373 u8 status[0x8]; 5374 u8 reserved_at_8[0x18]; 5375 5376 u8 syndrome[0x20]; 5377 5378 u8 reserved_at_40[0x1c0]; 5379 }; 5380 5381 enum { 5382 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5383 }; 5384 5385 enum { 5386 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5387 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5388 }; 5389 5390 struct mlx5_ifc_modify_scheduling_element_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 scheduling_hierarchy[0x8]; 5398 u8 reserved_at_48[0x18]; 5399 5400 u8 scheduling_element_id[0x20]; 5401 5402 u8 reserved_at_80[0x20]; 5403 5404 u8 modify_bitmask[0x20]; 5405 5406 u8 reserved_at_c0[0x40]; 5407 5408 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5409 5410 u8 reserved_at_300[0x100]; 5411 }; 5412 5413 struct mlx5_ifc_modify_rqt_out_bits { 5414 u8 status[0x8]; 5415 u8 reserved_0[0x18]; 5416 5417 u8 syndrome[0x20]; 5418 5419 u8 reserved_1[0x40]; 5420 }; 5421 5422 struct mlx5_ifc_modify_rqt_in_bits { 5423 u8 opcode[0x10]; 5424 u8 reserved_0[0x10]; 5425 5426 u8 reserved_1[0x10]; 5427 u8 op_mod[0x10]; 5428 5429 u8 reserved_2[0x8]; 5430 u8 rqtn[0x18]; 5431 5432 u8 reserved_3[0x20]; 5433 5434 u8 modify_bitmask[0x40]; 5435 5436 u8 reserved_4[0x40]; 5437 5438 struct mlx5_ifc_rqtc_bits ctx; 5439 }; 5440 5441 struct mlx5_ifc_modify_rq_out_bits { 5442 u8 status[0x8]; 5443 u8 reserved_0[0x18]; 5444 5445 u8 syndrome[0x20]; 5446 5447 u8 reserved_1[0x40]; 5448 }; 5449 5450 enum { 5451 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5452 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5453 }; 5454 5455 struct mlx5_ifc_modify_rq_in_bits { 5456 u8 opcode[0x10]; 5457 u8 reserved_0[0x10]; 5458 5459 u8 reserved_1[0x10]; 5460 u8 op_mod[0x10]; 5461 5462 u8 rq_state[0x4]; 5463 u8 reserved_2[0x4]; 5464 u8 rqn[0x18]; 5465 5466 u8 reserved_3[0x20]; 5467 5468 u8 modify_bitmask[0x40]; 5469 5470 u8 reserved_4[0x40]; 5471 5472 struct mlx5_ifc_rqc_bits ctx; 5473 }; 5474 5475 struct mlx5_ifc_modify_rmp_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_0[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_1[0x40]; 5482 }; 5483 5484 struct mlx5_ifc_rmp_bitmask_bits { 5485 u8 reserved[0x20]; 5486 5487 u8 reserved1[0x1f]; 5488 u8 lwm[0x1]; 5489 }; 5490 5491 struct mlx5_ifc_modify_rmp_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_0[0x10]; 5494 5495 u8 reserved_1[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 rmp_state[0x4]; 5499 u8 reserved_2[0x4]; 5500 u8 rmpn[0x18]; 5501 5502 u8 reserved_3[0x20]; 5503 5504 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5505 5506 u8 reserved_4[0x40]; 5507 5508 struct mlx5_ifc_rmpc_bits ctx; 5509 }; 5510 5511 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5512 u8 status[0x8]; 5513 u8 reserved_0[0x18]; 5514 5515 u8 syndrome[0x20]; 5516 5517 u8 reserved_1[0x40]; 5518 }; 5519 5520 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5521 u8 reserved_0[0x14]; 5522 u8 disable_uc_local_lb[0x1]; 5523 u8 disable_mc_local_lb[0x1]; 5524 u8 node_guid[0x1]; 5525 u8 port_guid[0x1]; 5526 u8 min_wqe_inline_mode[0x1]; 5527 u8 mtu[0x1]; 5528 u8 change_event[0x1]; 5529 u8 promisc[0x1]; 5530 u8 permanent_address[0x1]; 5531 u8 addresses_list[0x1]; 5532 u8 roce_en[0x1]; 5533 u8 reserved_1[0x1]; 5534 }; 5535 5536 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_0[0x10]; 5539 5540 u8 reserved_1[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 other_vport[0x1]; 5544 u8 reserved_2[0xf]; 5545 u8 vport_number[0x10]; 5546 5547 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5548 5549 u8 reserved_3[0x780]; 5550 5551 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5552 }; 5553 5554 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5555 u8 status[0x8]; 5556 u8 reserved_0[0x18]; 5557 5558 u8 syndrome[0x20]; 5559 5560 u8 reserved_1[0x40]; 5561 }; 5562 5563 struct mlx5_ifc_grh_bits { 5564 u8 ip_version[4]; 5565 u8 traffic_class[8]; 5566 u8 flow_label[20]; 5567 u8 payload_length[16]; 5568 u8 next_header[8]; 5569 u8 hop_limit[8]; 5570 u8 sgid[128]; 5571 u8 dgid[128]; 5572 }; 5573 5574 struct mlx5_ifc_bth_bits { 5575 u8 opcode[8]; 5576 u8 se[1]; 5577 u8 migreq[1]; 5578 u8 pad_count[2]; 5579 u8 tver[4]; 5580 u8 p_key[16]; 5581 u8 reserved8[8]; 5582 u8 dest_qp[24]; 5583 u8 ack_req[1]; 5584 u8 reserved7[7]; 5585 u8 psn[24]; 5586 }; 5587 5588 struct mlx5_ifc_aeth_bits { 5589 u8 syndrome[8]; 5590 u8 msn[24]; 5591 }; 5592 5593 struct mlx5_ifc_dceth_bits { 5594 u8 reserved0[8]; 5595 u8 session_id[24]; 5596 u8 reserved1[8]; 5597 u8 dci_dct[24]; 5598 }; 5599 5600 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5601 u8 opcode[0x10]; 5602 u8 reserved_0[0x10]; 5603 5604 u8 reserved_1[0x10]; 5605 u8 op_mod[0x10]; 5606 5607 u8 other_vport[0x1]; 5608 u8 reserved_2[0xb]; 5609 u8 port_num[0x4]; 5610 u8 vport_number[0x10]; 5611 5612 u8 reserved_3[0x20]; 5613 5614 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5615 }; 5616 5617 struct mlx5_ifc_modify_flow_table_out_bits { 5618 u8 status[0x8]; 5619 u8 reserved_at_8[0x18]; 5620 5621 u8 syndrome[0x20]; 5622 5623 u8 reserved_at_40[0x40]; 5624 }; 5625 5626 enum { 5627 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5628 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5629 }; 5630 5631 struct mlx5_ifc_modify_flow_table_in_bits { 5632 u8 opcode[0x10]; 5633 u8 reserved_at_10[0x10]; 5634 5635 u8 reserved_at_20[0x10]; 5636 u8 op_mod[0x10]; 5637 5638 u8 other_vport[0x1]; 5639 u8 reserved_at_41[0xf]; 5640 u8 vport_number[0x10]; 5641 5642 u8 reserved_at_60[0x10]; 5643 u8 modify_field_select[0x10]; 5644 5645 u8 table_type[0x8]; 5646 u8 reserved_at_88[0x18]; 5647 5648 u8 reserved_at_a0[0x8]; 5649 u8 table_id[0x18]; 5650 5651 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5652 }; 5653 5654 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5655 u8 status[0x8]; 5656 u8 reserved_0[0x18]; 5657 5658 u8 syndrome[0x20]; 5659 5660 u8 reserved_1[0x40]; 5661 }; 5662 5663 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5664 u8 reserved[0x1c]; 5665 u8 vport_cvlan_insert[0x1]; 5666 u8 vport_svlan_insert[0x1]; 5667 u8 vport_cvlan_strip[0x1]; 5668 u8 vport_svlan_strip[0x1]; 5669 }; 5670 5671 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5672 u8 opcode[0x10]; 5673 u8 reserved_0[0x10]; 5674 5675 u8 reserved_1[0x10]; 5676 u8 op_mod[0x10]; 5677 5678 u8 other_vport[0x1]; 5679 u8 reserved_2[0xf]; 5680 u8 vport_number[0x10]; 5681 5682 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5683 5684 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5685 }; 5686 5687 struct mlx5_ifc_modify_cq_out_bits { 5688 u8 status[0x8]; 5689 u8 reserved_0[0x18]; 5690 5691 u8 syndrome[0x20]; 5692 5693 u8 reserved_1[0x40]; 5694 }; 5695 5696 enum { 5697 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5698 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5699 }; 5700 5701 struct mlx5_ifc_modify_cq_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_0[0x10]; 5704 5705 u8 reserved_1[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 reserved_2[0x8]; 5709 u8 cqn[0x18]; 5710 5711 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5712 5713 struct mlx5_ifc_cqc_bits cq_context; 5714 5715 u8 reserved_3[0x600]; 5716 5717 u8 pas[0][0x40]; 5718 }; 5719 5720 struct mlx5_ifc_modify_cong_status_out_bits { 5721 u8 status[0x8]; 5722 u8 reserved_0[0x18]; 5723 5724 u8 syndrome[0x20]; 5725 5726 u8 reserved_1[0x40]; 5727 }; 5728 5729 struct mlx5_ifc_modify_cong_status_in_bits { 5730 u8 opcode[0x10]; 5731 u8 reserved_0[0x10]; 5732 5733 u8 reserved_1[0x10]; 5734 u8 op_mod[0x10]; 5735 5736 u8 reserved_2[0x18]; 5737 u8 priority[0x4]; 5738 u8 cong_protocol[0x4]; 5739 5740 u8 enable[0x1]; 5741 u8 tag_enable[0x1]; 5742 u8 reserved_3[0x1e]; 5743 }; 5744 5745 struct mlx5_ifc_modify_cong_params_out_bits { 5746 u8 status[0x8]; 5747 u8 reserved_0[0x18]; 5748 5749 u8 syndrome[0x20]; 5750 5751 u8 reserved_1[0x40]; 5752 }; 5753 5754 struct mlx5_ifc_modify_cong_params_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_0[0x10]; 5757 5758 u8 reserved_1[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 reserved_2[0x1c]; 5762 u8 cong_protocol[0x4]; 5763 5764 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5765 5766 u8 reserved_3[0x80]; 5767 5768 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5769 }; 5770 5771 struct mlx5_ifc_manage_pages_out_bits { 5772 u8 status[0x8]; 5773 u8 reserved_0[0x18]; 5774 5775 u8 syndrome[0x20]; 5776 5777 u8 output_num_entries[0x20]; 5778 5779 u8 reserved_1[0x20]; 5780 5781 u8 pas[0][0x40]; 5782 }; 5783 5784 enum { 5785 MLX5_PAGES_CANT_GIVE = 0x0, 5786 MLX5_PAGES_GIVE = 0x1, 5787 MLX5_PAGES_TAKE = 0x2, 5788 }; 5789 5790 struct mlx5_ifc_manage_pages_in_bits { 5791 u8 opcode[0x10]; 5792 u8 reserved_0[0x10]; 5793 5794 u8 reserved_1[0x10]; 5795 u8 op_mod[0x10]; 5796 5797 u8 reserved_2[0x10]; 5798 u8 function_id[0x10]; 5799 5800 u8 input_num_entries[0x20]; 5801 5802 u8 pas[0][0x40]; 5803 }; 5804 5805 struct mlx5_ifc_mad_ifc_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_0[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_1[0x40]; 5812 5813 u8 response_mad_packet[256][0x8]; 5814 }; 5815 5816 struct mlx5_ifc_mad_ifc_in_bits { 5817 u8 opcode[0x10]; 5818 u8 reserved_0[0x10]; 5819 5820 u8 reserved_1[0x10]; 5821 u8 op_mod[0x10]; 5822 5823 u8 remote_lid[0x10]; 5824 u8 reserved_2[0x8]; 5825 u8 port[0x8]; 5826 5827 u8 reserved_3[0x20]; 5828 5829 u8 mad[256][0x8]; 5830 }; 5831 5832 struct mlx5_ifc_init_hca_out_bits { 5833 u8 status[0x8]; 5834 u8 reserved_0[0x18]; 5835 5836 u8 syndrome[0x20]; 5837 5838 u8 reserved_1[0x40]; 5839 }; 5840 5841 enum { 5842 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5843 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5844 }; 5845 5846 struct mlx5_ifc_init_hca_in_bits { 5847 u8 opcode[0x10]; 5848 u8 reserved_0[0x10]; 5849 5850 u8 reserved_1[0x10]; 5851 u8 op_mod[0x10]; 5852 5853 u8 reserved_2[0x40]; 5854 }; 5855 5856 struct mlx5_ifc_init2rtr_qp_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_0[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_1[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_init2rtr_qp_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_0[0x10]; 5868 5869 u8 reserved_1[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 reserved_2[0x8]; 5873 u8 qpn[0x18]; 5874 5875 u8 reserved_3[0x20]; 5876 5877 u8 opt_param_mask[0x20]; 5878 5879 u8 reserved_4[0x20]; 5880 5881 struct mlx5_ifc_qpc_bits qpc; 5882 5883 u8 reserved_5[0x80]; 5884 }; 5885 5886 struct mlx5_ifc_init2init_qp_out_bits { 5887 u8 status[0x8]; 5888 u8 reserved_0[0x18]; 5889 5890 u8 syndrome[0x20]; 5891 5892 u8 reserved_1[0x40]; 5893 }; 5894 5895 struct mlx5_ifc_init2init_qp_in_bits { 5896 u8 opcode[0x10]; 5897 u8 reserved_0[0x10]; 5898 5899 u8 reserved_1[0x10]; 5900 u8 op_mod[0x10]; 5901 5902 u8 reserved_2[0x8]; 5903 u8 qpn[0x18]; 5904 5905 u8 reserved_3[0x20]; 5906 5907 u8 opt_param_mask[0x20]; 5908 5909 u8 reserved_4[0x20]; 5910 5911 struct mlx5_ifc_qpc_bits qpc; 5912 5913 u8 reserved_5[0x80]; 5914 }; 5915 5916 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_0[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_1[0x40]; 5923 5924 u8 packet_headers_log[128][0x8]; 5925 5926 u8 packet_syndrome[64][0x8]; 5927 }; 5928 5929 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5930 u8 opcode[0x10]; 5931 u8 reserved_0[0x10]; 5932 5933 u8 reserved_1[0x10]; 5934 u8 op_mod[0x10]; 5935 5936 u8 reserved_2[0x40]; 5937 }; 5938 5939 struct mlx5_ifc_gen_eqe_in_bits { 5940 u8 opcode[0x10]; 5941 u8 reserved_0[0x10]; 5942 5943 u8 reserved_1[0x10]; 5944 u8 op_mod[0x10]; 5945 5946 u8 reserved_2[0x18]; 5947 u8 eq_number[0x8]; 5948 5949 u8 reserved_3[0x20]; 5950 5951 u8 eqe[64][0x8]; 5952 }; 5953 5954 struct mlx5_ifc_gen_eq_out_bits { 5955 u8 status[0x8]; 5956 u8 reserved_0[0x18]; 5957 5958 u8 syndrome[0x20]; 5959 5960 u8 reserved_1[0x40]; 5961 }; 5962 5963 struct mlx5_ifc_enable_hca_out_bits { 5964 u8 status[0x8]; 5965 u8 reserved_0[0x18]; 5966 5967 u8 syndrome[0x20]; 5968 5969 u8 reserved_1[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_enable_hca_in_bits { 5973 u8 opcode[0x10]; 5974 u8 reserved_0[0x10]; 5975 5976 u8 reserved_1[0x10]; 5977 u8 op_mod[0x10]; 5978 5979 u8 reserved_2[0x10]; 5980 u8 function_id[0x10]; 5981 5982 u8 reserved_3[0x20]; 5983 }; 5984 5985 struct mlx5_ifc_drain_dct_out_bits { 5986 u8 status[0x8]; 5987 u8 reserved_0[0x18]; 5988 5989 u8 syndrome[0x20]; 5990 5991 u8 reserved_1[0x40]; 5992 }; 5993 5994 struct mlx5_ifc_drain_dct_in_bits { 5995 u8 opcode[0x10]; 5996 u8 reserved_0[0x10]; 5997 5998 u8 reserved_1[0x10]; 5999 u8 op_mod[0x10]; 6000 6001 u8 reserved_2[0x8]; 6002 u8 dctn[0x18]; 6003 6004 u8 reserved_3[0x20]; 6005 }; 6006 6007 struct mlx5_ifc_disable_hca_out_bits { 6008 u8 status[0x8]; 6009 u8 reserved_0[0x18]; 6010 6011 u8 syndrome[0x20]; 6012 6013 u8 reserved_1[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_disable_hca_in_bits { 6017 u8 opcode[0x10]; 6018 u8 reserved_0[0x10]; 6019 6020 u8 reserved_1[0x10]; 6021 u8 op_mod[0x10]; 6022 6023 u8 reserved_2[0x10]; 6024 u8 function_id[0x10]; 6025 6026 u8 reserved_3[0x20]; 6027 }; 6028 6029 struct mlx5_ifc_detach_from_mcg_out_bits { 6030 u8 status[0x8]; 6031 u8 reserved_0[0x18]; 6032 6033 u8 syndrome[0x20]; 6034 6035 u8 reserved_1[0x40]; 6036 }; 6037 6038 struct mlx5_ifc_detach_from_mcg_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_0[0x10]; 6041 6042 u8 reserved_1[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_2[0x8]; 6046 u8 qpn[0x18]; 6047 6048 u8 reserved_3[0x20]; 6049 6050 u8 multicast_gid[16][0x8]; 6051 }; 6052 6053 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6054 u8 status[0x8]; 6055 u8 reserved_0[0x18]; 6056 6057 u8 syndrome[0x20]; 6058 6059 u8 reserved_1[0x40]; 6060 }; 6061 6062 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6063 u8 opcode[0x10]; 6064 u8 reserved_0[0x10]; 6065 6066 u8 reserved_1[0x10]; 6067 u8 op_mod[0x10]; 6068 6069 u8 reserved_2[0x8]; 6070 u8 xrc_srqn[0x18]; 6071 6072 u8 reserved_3[0x20]; 6073 }; 6074 6075 struct mlx5_ifc_destroy_tis_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_0[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_1[0x40]; 6082 }; 6083 6084 struct mlx5_ifc_destroy_tis_in_bits { 6085 u8 opcode[0x10]; 6086 u8 reserved_0[0x10]; 6087 6088 u8 reserved_1[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 reserved_2[0x8]; 6092 u8 tisn[0x18]; 6093 6094 u8 reserved_3[0x20]; 6095 }; 6096 6097 struct mlx5_ifc_destroy_tir_out_bits { 6098 u8 status[0x8]; 6099 u8 reserved_0[0x18]; 6100 6101 u8 syndrome[0x20]; 6102 6103 u8 reserved_1[0x40]; 6104 }; 6105 6106 struct mlx5_ifc_destroy_tir_in_bits { 6107 u8 opcode[0x10]; 6108 u8 reserved_0[0x10]; 6109 6110 u8 reserved_1[0x10]; 6111 u8 op_mod[0x10]; 6112 6113 u8 reserved_2[0x8]; 6114 u8 tirn[0x18]; 6115 6116 u8 reserved_3[0x20]; 6117 }; 6118 6119 struct mlx5_ifc_destroy_srq_out_bits { 6120 u8 status[0x8]; 6121 u8 reserved_0[0x18]; 6122 6123 u8 syndrome[0x20]; 6124 6125 u8 reserved_1[0x40]; 6126 }; 6127 6128 struct mlx5_ifc_destroy_srq_in_bits { 6129 u8 opcode[0x10]; 6130 u8 reserved_0[0x10]; 6131 6132 u8 reserved_1[0x10]; 6133 u8 op_mod[0x10]; 6134 6135 u8 reserved_2[0x8]; 6136 u8 srqn[0x18]; 6137 6138 u8 reserved_3[0x20]; 6139 }; 6140 6141 struct mlx5_ifc_destroy_sq_out_bits { 6142 u8 status[0x8]; 6143 u8 reserved_0[0x18]; 6144 6145 u8 syndrome[0x20]; 6146 6147 u8 reserved_1[0x40]; 6148 }; 6149 6150 struct mlx5_ifc_destroy_sq_in_bits { 6151 u8 opcode[0x10]; 6152 u8 reserved_0[0x10]; 6153 6154 u8 reserved_1[0x10]; 6155 u8 op_mod[0x10]; 6156 6157 u8 reserved_2[0x8]; 6158 u8 sqn[0x18]; 6159 6160 u8 reserved_3[0x20]; 6161 }; 6162 6163 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6164 u8 status[0x8]; 6165 u8 reserved_at_8[0x18]; 6166 6167 u8 syndrome[0x20]; 6168 6169 u8 reserved_at_40[0x1c0]; 6170 }; 6171 6172 enum { 6173 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6174 }; 6175 6176 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6177 u8 opcode[0x10]; 6178 u8 reserved_at_10[0x10]; 6179 6180 u8 reserved_at_20[0x10]; 6181 u8 op_mod[0x10]; 6182 6183 u8 scheduling_hierarchy[0x8]; 6184 u8 reserved_at_48[0x18]; 6185 6186 u8 scheduling_element_id[0x20]; 6187 6188 u8 reserved_at_80[0x180]; 6189 }; 6190 6191 struct mlx5_ifc_destroy_rqt_out_bits { 6192 u8 status[0x8]; 6193 u8 reserved_0[0x18]; 6194 6195 u8 syndrome[0x20]; 6196 6197 u8 reserved_1[0x40]; 6198 }; 6199 6200 struct mlx5_ifc_destroy_rqt_in_bits { 6201 u8 opcode[0x10]; 6202 u8 reserved_0[0x10]; 6203 6204 u8 reserved_1[0x10]; 6205 u8 op_mod[0x10]; 6206 6207 u8 reserved_2[0x8]; 6208 u8 rqtn[0x18]; 6209 6210 u8 reserved_3[0x20]; 6211 }; 6212 6213 struct mlx5_ifc_destroy_rq_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_0[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 reserved_1[0x40]; 6220 }; 6221 6222 struct mlx5_ifc_destroy_rq_in_bits { 6223 u8 opcode[0x10]; 6224 u8 reserved_0[0x10]; 6225 6226 u8 reserved_1[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_2[0x8]; 6230 u8 rqn[0x18]; 6231 6232 u8 reserved_3[0x20]; 6233 }; 6234 6235 struct mlx5_ifc_destroy_rmp_out_bits { 6236 u8 status[0x8]; 6237 u8 reserved_0[0x18]; 6238 6239 u8 syndrome[0x20]; 6240 6241 u8 reserved_1[0x40]; 6242 }; 6243 6244 struct mlx5_ifc_destroy_rmp_in_bits { 6245 u8 opcode[0x10]; 6246 u8 reserved_0[0x10]; 6247 6248 u8 reserved_1[0x10]; 6249 u8 op_mod[0x10]; 6250 6251 u8 reserved_2[0x8]; 6252 u8 rmpn[0x18]; 6253 6254 u8 reserved_3[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_destroy_qp_out_bits { 6258 u8 status[0x8]; 6259 u8 reserved_0[0x18]; 6260 6261 u8 syndrome[0x20]; 6262 6263 u8 reserved_1[0x40]; 6264 }; 6265 6266 struct mlx5_ifc_destroy_qp_in_bits { 6267 u8 opcode[0x10]; 6268 u8 reserved_0[0x10]; 6269 6270 u8 reserved_1[0x10]; 6271 u8 op_mod[0x10]; 6272 6273 u8 reserved_2[0x8]; 6274 u8 qpn[0x18]; 6275 6276 u8 reserved_3[0x20]; 6277 }; 6278 6279 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6280 u8 status[0x8]; 6281 u8 reserved_at_8[0x18]; 6282 6283 u8 syndrome[0x20]; 6284 6285 u8 reserved_at_40[0x1c0]; 6286 }; 6287 6288 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6289 u8 opcode[0x10]; 6290 u8 reserved_at_10[0x10]; 6291 6292 u8 reserved_at_20[0x10]; 6293 u8 op_mod[0x10]; 6294 6295 u8 reserved_at_40[0x20]; 6296 6297 u8 reserved_at_60[0x10]; 6298 u8 qos_para_vport_number[0x10]; 6299 6300 u8 reserved_at_80[0x180]; 6301 }; 6302 6303 struct mlx5_ifc_destroy_psv_out_bits { 6304 u8 status[0x8]; 6305 u8 reserved_0[0x18]; 6306 6307 u8 syndrome[0x20]; 6308 6309 u8 reserved_1[0x40]; 6310 }; 6311 6312 struct mlx5_ifc_destroy_psv_in_bits { 6313 u8 opcode[0x10]; 6314 u8 reserved_0[0x10]; 6315 6316 u8 reserved_1[0x10]; 6317 u8 op_mod[0x10]; 6318 6319 u8 reserved_2[0x8]; 6320 u8 psvn[0x18]; 6321 6322 u8 reserved_3[0x20]; 6323 }; 6324 6325 struct mlx5_ifc_destroy_mkey_out_bits { 6326 u8 status[0x8]; 6327 u8 reserved_0[0x18]; 6328 6329 u8 syndrome[0x20]; 6330 6331 u8 reserved_1[0x40]; 6332 }; 6333 6334 struct mlx5_ifc_destroy_mkey_in_bits { 6335 u8 opcode[0x10]; 6336 u8 reserved_0[0x10]; 6337 6338 u8 reserved_1[0x10]; 6339 u8 op_mod[0x10]; 6340 6341 u8 reserved_2[0x8]; 6342 u8 mkey_index[0x18]; 6343 6344 u8 reserved_3[0x20]; 6345 }; 6346 6347 struct mlx5_ifc_destroy_flow_table_out_bits { 6348 u8 status[0x8]; 6349 u8 reserved_0[0x18]; 6350 6351 u8 syndrome[0x20]; 6352 6353 u8 reserved_1[0x40]; 6354 }; 6355 6356 struct mlx5_ifc_destroy_flow_table_in_bits { 6357 u8 opcode[0x10]; 6358 u8 reserved_0[0x10]; 6359 6360 u8 reserved_1[0x10]; 6361 u8 op_mod[0x10]; 6362 6363 u8 other_vport[0x1]; 6364 u8 reserved_2[0xf]; 6365 u8 vport_number[0x10]; 6366 6367 u8 reserved_3[0x20]; 6368 6369 u8 table_type[0x8]; 6370 u8 reserved_4[0x18]; 6371 6372 u8 reserved_5[0x8]; 6373 u8 table_id[0x18]; 6374 6375 u8 reserved_6[0x140]; 6376 }; 6377 6378 struct mlx5_ifc_destroy_flow_group_out_bits { 6379 u8 status[0x8]; 6380 u8 reserved_0[0x18]; 6381 6382 u8 syndrome[0x20]; 6383 6384 u8 reserved_1[0x40]; 6385 }; 6386 6387 struct mlx5_ifc_destroy_flow_group_in_bits { 6388 u8 opcode[0x10]; 6389 u8 reserved_0[0x10]; 6390 6391 u8 reserved_1[0x10]; 6392 u8 op_mod[0x10]; 6393 6394 u8 other_vport[0x1]; 6395 u8 reserved_2[0xf]; 6396 u8 vport_number[0x10]; 6397 6398 u8 reserved_3[0x20]; 6399 6400 u8 table_type[0x8]; 6401 u8 reserved_4[0x18]; 6402 6403 u8 reserved_5[0x8]; 6404 u8 table_id[0x18]; 6405 6406 u8 group_id[0x20]; 6407 6408 u8 reserved_6[0x120]; 6409 }; 6410 6411 struct mlx5_ifc_destroy_eq_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_0[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_1[0x40]; 6418 }; 6419 6420 struct mlx5_ifc_destroy_eq_in_bits { 6421 u8 opcode[0x10]; 6422 u8 reserved_0[0x10]; 6423 6424 u8 reserved_1[0x10]; 6425 u8 op_mod[0x10]; 6426 6427 u8 reserved_2[0x18]; 6428 u8 eq_number[0x8]; 6429 6430 u8 reserved_3[0x20]; 6431 }; 6432 6433 struct mlx5_ifc_destroy_dct_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_0[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_1[0x40]; 6440 }; 6441 6442 struct mlx5_ifc_destroy_dct_in_bits { 6443 u8 opcode[0x10]; 6444 u8 reserved_0[0x10]; 6445 6446 u8 reserved_1[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 reserved_2[0x8]; 6450 u8 dctn[0x18]; 6451 6452 u8 reserved_3[0x20]; 6453 }; 6454 6455 struct mlx5_ifc_destroy_cq_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_0[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_1[0x40]; 6462 }; 6463 6464 struct mlx5_ifc_destroy_cq_in_bits { 6465 u8 opcode[0x10]; 6466 u8 reserved_0[0x10]; 6467 6468 u8 reserved_1[0x10]; 6469 u8 op_mod[0x10]; 6470 6471 u8 reserved_2[0x8]; 6472 u8 cqn[0x18]; 6473 6474 u8 reserved_3[0x20]; 6475 }; 6476 6477 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6478 u8 status[0x8]; 6479 u8 reserved_0[0x18]; 6480 6481 u8 syndrome[0x20]; 6482 6483 u8 reserved_1[0x40]; 6484 }; 6485 6486 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6487 u8 opcode[0x10]; 6488 u8 reserved_0[0x10]; 6489 6490 u8 reserved_1[0x10]; 6491 u8 op_mod[0x10]; 6492 6493 u8 reserved_2[0x20]; 6494 6495 u8 reserved_3[0x10]; 6496 u8 vxlan_udp_port[0x10]; 6497 }; 6498 6499 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_0[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_1[0x40]; 6506 }; 6507 6508 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6509 u8 opcode[0x10]; 6510 u8 reserved_0[0x10]; 6511 6512 u8 reserved_1[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 reserved_2[0x60]; 6516 6517 u8 reserved_3[0x8]; 6518 u8 table_index[0x18]; 6519 6520 u8 reserved_4[0x140]; 6521 }; 6522 6523 struct mlx5_ifc_delete_fte_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_0[0x18]; 6526 6527 u8 syndrome[0x20]; 6528 6529 u8 reserved_1[0x40]; 6530 }; 6531 6532 struct mlx5_ifc_delete_fte_in_bits { 6533 u8 opcode[0x10]; 6534 u8 reserved_0[0x10]; 6535 6536 u8 reserved_1[0x10]; 6537 u8 op_mod[0x10]; 6538 6539 u8 other_vport[0x1]; 6540 u8 reserved_2[0xf]; 6541 u8 vport_number[0x10]; 6542 6543 u8 reserved_3[0x20]; 6544 6545 u8 table_type[0x8]; 6546 u8 reserved_4[0x18]; 6547 6548 u8 reserved_5[0x8]; 6549 u8 table_id[0x18]; 6550 6551 u8 reserved_6[0x40]; 6552 6553 u8 flow_index[0x20]; 6554 6555 u8 reserved_7[0xe0]; 6556 }; 6557 6558 struct mlx5_ifc_dealloc_xrcd_out_bits { 6559 u8 status[0x8]; 6560 u8 reserved_0[0x18]; 6561 6562 u8 syndrome[0x20]; 6563 6564 u8 reserved_1[0x40]; 6565 }; 6566 6567 struct mlx5_ifc_dealloc_xrcd_in_bits { 6568 u8 opcode[0x10]; 6569 u8 reserved_0[0x10]; 6570 6571 u8 reserved_1[0x10]; 6572 u8 op_mod[0x10]; 6573 6574 u8 reserved_2[0x8]; 6575 u8 xrcd[0x18]; 6576 6577 u8 reserved_3[0x20]; 6578 }; 6579 6580 struct mlx5_ifc_dealloc_uar_out_bits { 6581 u8 status[0x8]; 6582 u8 reserved_0[0x18]; 6583 6584 u8 syndrome[0x20]; 6585 6586 u8 reserved_1[0x40]; 6587 }; 6588 6589 struct mlx5_ifc_dealloc_uar_in_bits { 6590 u8 opcode[0x10]; 6591 u8 reserved_0[0x10]; 6592 6593 u8 reserved_1[0x10]; 6594 u8 op_mod[0x10]; 6595 6596 u8 reserved_2[0x8]; 6597 u8 uar[0x18]; 6598 6599 u8 reserved_3[0x20]; 6600 }; 6601 6602 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6603 u8 status[0x8]; 6604 u8 reserved_0[0x18]; 6605 6606 u8 syndrome[0x20]; 6607 6608 u8 reserved_1[0x40]; 6609 }; 6610 6611 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6612 u8 opcode[0x10]; 6613 u8 reserved_0[0x10]; 6614 6615 u8 reserved_1[0x10]; 6616 u8 op_mod[0x10]; 6617 6618 u8 reserved_2[0x8]; 6619 u8 transport_domain[0x18]; 6620 6621 u8 reserved_3[0x20]; 6622 }; 6623 6624 struct mlx5_ifc_dealloc_q_counter_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_0[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_1[0x40]; 6631 }; 6632 6633 struct mlx5_ifc_counter_id_bits { 6634 u8 reserved[0x10]; 6635 u8 counter_id[0x10]; 6636 }; 6637 6638 struct mlx5_ifc_diagnostic_params_context_bits { 6639 u8 num_of_counters[0x10]; 6640 u8 reserved_2[0x8]; 6641 u8 log_num_of_samples[0x8]; 6642 6643 u8 single[0x1]; 6644 u8 repetitive[0x1]; 6645 u8 sync[0x1]; 6646 u8 clear[0x1]; 6647 u8 on_demand[0x1]; 6648 u8 enable[0x1]; 6649 u8 reserved_3[0x12]; 6650 u8 log_sample_period[0x8]; 6651 6652 u8 reserved_4[0x80]; 6653 6654 struct mlx5_ifc_counter_id_bits counter_id[0]; 6655 }; 6656 6657 struct mlx5_ifc_set_diagnostic_params_in_bits { 6658 u8 opcode[0x10]; 6659 u8 reserved_0[0x10]; 6660 6661 u8 reserved_1[0x10]; 6662 u8 op_mod[0x10]; 6663 6664 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6665 }; 6666 6667 struct mlx5_ifc_set_diagnostic_params_out_bits { 6668 u8 status[0x8]; 6669 u8 reserved_0[0x18]; 6670 6671 u8 syndrome[0x20]; 6672 6673 u8 reserved_1[0x40]; 6674 }; 6675 6676 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_0[0x10]; 6679 6680 u8 reserved_1[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 num_of_samples[0x10]; 6684 u8 sample_index[0x10]; 6685 6686 u8 reserved_2[0x20]; 6687 }; 6688 6689 struct mlx5_ifc_diagnostic_counter_bits { 6690 u8 counter_id[0x10]; 6691 u8 sample_id[0x10]; 6692 6693 u8 time_stamp_31_0[0x20]; 6694 6695 u8 counter_value_h[0x20]; 6696 6697 u8 counter_value_l[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_0[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_1[0x40]; 6707 6708 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6709 }; 6710 6711 struct mlx5_ifc_dealloc_q_counter_in_bits { 6712 u8 opcode[0x10]; 6713 u8 reserved_0[0x10]; 6714 6715 u8 reserved_1[0x10]; 6716 u8 op_mod[0x10]; 6717 6718 u8 reserved_2[0x18]; 6719 u8 counter_set_id[0x8]; 6720 6721 u8 reserved_3[0x20]; 6722 }; 6723 6724 struct mlx5_ifc_dealloc_pd_out_bits { 6725 u8 status[0x8]; 6726 u8 reserved_0[0x18]; 6727 6728 u8 syndrome[0x20]; 6729 6730 u8 reserved_1[0x40]; 6731 }; 6732 6733 struct mlx5_ifc_dealloc_pd_in_bits { 6734 u8 opcode[0x10]; 6735 u8 reserved_0[0x10]; 6736 6737 u8 reserved_1[0x10]; 6738 u8 op_mod[0x10]; 6739 6740 u8 reserved_2[0x8]; 6741 u8 pd[0x18]; 6742 6743 u8 reserved_3[0x20]; 6744 }; 6745 6746 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6747 u8 status[0x8]; 6748 u8 reserved_0[0x18]; 6749 6750 u8 syndrome[0x20]; 6751 6752 u8 reserved_1[0x40]; 6753 }; 6754 6755 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6756 u8 opcode[0x10]; 6757 u8 reserved_0[0x10]; 6758 6759 u8 reserved_1[0x10]; 6760 u8 op_mod[0x10]; 6761 6762 u8 reserved_2[0x10]; 6763 u8 flow_counter_id[0x10]; 6764 6765 u8 reserved_3[0x20]; 6766 }; 6767 6768 struct mlx5_ifc_deactivate_tracer_out_bits { 6769 u8 status[0x8]; 6770 u8 reserved_0[0x18]; 6771 6772 u8 syndrome[0x20]; 6773 6774 u8 reserved_1[0x40]; 6775 }; 6776 6777 struct mlx5_ifc_deactivate_tracer_in_bits { 6778 u8 opcode[0x10]; 6779 u8 reserved_0[0x10]; 6780 6781 u8 reserved_1[0x10]; 6782 u8 op_mod[0x10]; 6783 6784 u8 mkey[0x20]; 6785 6786 u8 reserved_2[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_create_xrc_srq_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_0[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_1[0x8]; 6796 u8 xrc_srqn[0x18]; 6797 6798 u8 reserved_2[0x20]; 6799 }; 6800 6801 struct mlx5_ifc_create_xrc_srq_in_bits { 6802 u8 opcode[0x10]; 6803 u8 reserved_0[0x10]; 6804 6805 u8 reserved_1[0x10]; 6806 u8 op_mod[0x10]; 6807 6808 u8 reserved_2[0x40]; 6809 6810 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6811 6812 u8 reserved_3[0x600]; 6813 6814 u8 pas[0][0x40]; 6815 }; 6816 6817 struct mlx5_ifc_create_tis_out_bits { 6818 u8 status[0x8]; 6819 u8 reserved_0[0x18]; 6820 6821 u8 syndrome[0x20]; 6822 6823 u8 reserved_1[0x8]; 6824 u8 tisn[0x18]; 6825 6826 u8 reserved_2[0x20]; 6827 }; 6828 6829 struct mlx5_ifc_create_tis_in_bits { 6830 u8 opcode[0x10]; 6831 u8 reserved_0[0x10]; 6832 6833 u8 reserved_1[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 reserved_2[0xc0]; 6837 6838 struct mlx5_ifc_tisc_bits ctx; 6839 }; 6840 6841 struct mlx5_ifc_create_tir_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_0[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_1[0x8]; 6848 u8 tirn[0x18]; 6849 6850 u8 reserved_2[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_create_tir_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_0[0x10]; 6856 6857 u8 reserved_1[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_2[0xc0]; 6861 6862 struct mlx5_ifc_tirc_bits tir_context; 6863 }; 6864 6865 struct mlx5_ifc_create_srq_out_bits { 6866 u8 status[0x8]; 6867 u8 reserved_0[0x18]; 6868 6869 u8 syndrome[0x20]; 6870 6871 u8 reserved_1[0x8]; 6872 u8 srqn[0x18]; 6873 6874 u8 reserved_2[0x20]; 6875 }; 6876 6877 struct mlx5_ifc_create_srq_in_bits { 6878 u8 opcode[0x10]; 6879 u8 reserved_0[0x10]; 6880 6881 u8 reserved_1[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 reserved_2[0x40]; 6885 6886 struct mlx5_ifc_srqc_bits srq_context_entry; 6887 6888 u8 reserved_3[0x600]; 6889 6890 u8 pas[0][0x40]; 6891 }; 6892 6893 struct mlx5_ifc_create_sq_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_0[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_1[0x8]; 6900 u8 sqn[0x18]; 6901 6902 u8 reserved_2[0x20]; 6903 }; 6904 6905 struct mlx5_ifc_create_sq_in_bits { 6906 u8 opcode[0x10]; 6907 u8 reserved_0[0x10]; 6908 6909 u8 reserved_1[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 reserved_2[0xc0]; 6913 6914 struct mlx5_ifc_sqc_bits ctx; 6915 }; 6916 6917 struct mlx5_ifc_create_scheduling_element_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x40]; 6924 6925 u8 scheduling_element_id[0x20]; 6926 6927 u8 reserved_at_a0[0x160]; 6928 }; 6929 6930 enum { 6931 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6932 }; 6933 6934 struct mlx5_ifc_create_scheduling_element_in_bits { 6935 u8 opcode[0x10]; 6936 u8 reserved_at_10[0x10]; 6937 6938 u8 reserved_at_20[0x10]; 6939 u8 op_mod[0x10]; 6940 6941 u8 scheduling_hierarchy[0x8]; 6942 u8 reserved_at_48[0x18]; 6943 6944 u8 reserved_at_60[0xa0]; 6945 6946 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6947 6948 u8 reserved_at_300[0x100]; 6949 }; 6950 6951 struct mlx5_ifc_create_rqt_out_bits { 6952 u8 status[0x8]; 6953 u8 reserved_0[0x18]; 6954 6955 u8 syndrome[0x20]; 6956 6957 u8 reserved_1[0x8]; 6958 u8 rqtn[0x18]; 6959 6960 u8 reserved_2[0x20]; 6961 }; 6962 6963 struct mlx5_ifc_create_rqt_in_bits { 6964 u8 opcode[0x10]; 6965 u8 reserved_0[0x10]; 6966 6967 u8 reserved_1[0x10]; 6968 u8 op_mod[0x10]; 6969 6970 u8 reserved_2[0xc0]; 6971 6972 struct mlx5_ifc_rqtc_bits rqt_context; 6973 }; 6974 6975 struct mlx5_ifc_create_rq_out_bits { 6976 u8 status[0x8]; 6977 u8 reserved_0[0x18]; 6978 6979 u8 syndrome[0x20]; 6980 6981 u8 reserved_1[0x8]; 6982 u8 rqn[0x18]; 6983 6984 u8 reserved_2[0x20]; 6985 }; 6986 6987 struct mlx5_ifc_create_rq_in_bits { 6988 u8 opcode[0x10]; 6989 u8 reserved_0[0x10]; 6990 6991 u8 reserved_1[0x10]; 6992 u8 op_mod[0x10]; 6993 6994 u8 reserved_2[0xc0]; 6995 6996 struct mlx5_ifc_rqc_bits ctx; 6997 }; 6998 6999 struct mlx5_ifc_create_rmp_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_0[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_1[0x8]; 7006 u8 rmpn[0x18]; 7007 7008 u8 reserved_2[0x20]; 7009 }; 7010 7011 struct mlx5_ifc_create_rmp_in_bits { 7012 u8 opcode[0x10]; 7013 u8 reserved_0[0x10]; 7014 7015 u8 reserved_1[0x10]; 7016 u8 op_mod[0x10]; 7017 7018 u8 reserved_2[0xc0]; 7019 7020 struct mlx5_ifc_rmpc_bits ctx; 7021 }; 7022 7023 struct mlx5_ifc_create_qp_out_bits { 7024 u8 status[0x8]; 7025 u8 reserved_0[0x18]; 7026 7027 u8 syndrome[0x20]; 7028 7029 u8 reserved_1[0x8]; 7030 u8 qpn[0x18]; 7031 7032 u8 reserved_2[0x20]; 7033 }; 7034 7035 struct mlx5_ifc_create_qp_in_bits { 7036 u8 opcode[0x10]; 7037 u8 reserved_0[0x10]; 7038 7039 u8 reserved_1[0x10]; 7040 u8 op_mod[0x10]; 7041 7042 u8 reserved_2[0x8]; 7043 u8 input_qpn[0x18]; 7044 7045 u8 reserved_3[0x20]; 7046 7047 u8 opt_param_mask[0x20]; 7048 7049 u8 reserved_4[0x20]; 7050 7051 struct mlx5_ifc_qpc_bits qpc; 7052 7053 u8 reserved_5[0x80]; 7054 7055 u8 pas[0][0x40]; 7056 }; 7057 7058 struct mlx5_ifc_create_qos_para_vport_out_bits { 7059 u8 status[0x8]; 7060 u8 reserved_at_8[0x18]; 7061 7062 u8 syndrome[0x20]; 7063 7064 u8 reserved_at_40[0x20]; 7065 7066 u8 reserved_at_60[0x10]; 7067 u8 qos_para_vport_number[0x10]; 7068 7069 u8 reserved_at_80[0x180]; 7070 }; 7071 7072 struct mlx5_ifc_create_qos_para_vport_in_bits { 7073 u8 opcode[0x10]; 7074 u8 reserved_at_10[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 reserved_at_40[0x1c0]; 7080 }; 7081 7082 struct mlx5_ifc_create_psv_out_bits { 7083 u8 status[0x8]; 7084 u8 reserved_0[0x18]; 7085 7086 u8 syndrome[0x20]; 7087 7088 u8 reserved_1[0x40]; 7089 7090 u8 reserved_2[0x8]; 7091 u8 psv0_index[0x18]; 7092 7093 u8 reserved_3[0x8]; 7094 u8 psv1_index[0x18]; 7095 7096 u8 reserved_4[0x8]; 7097 u8 psv2_index[0x18]; 7098 7099 u8 reserved_5[0x8]; 7100 u8 psv3_index[0x18]; 7101 }; 7102 7103 struct mlx5_ifc_create_psv_in_bits { 7104 u8 opcode[0x10]; 7105 u8 reserved_0[0x10]; 7106 7107 u8 reserved_1[0x10]; 7108 u8 op_mod[0x10]; 7109 7110 u8 num_psv[0x4]; 7111 u8 reserved_2[0x4]; 7112 u8 pd[0x18]; 7113 7114 u8 reserved_3[0x20]; 7115 }; 7116 7117 struct mlx5_ifc_create_mkey_out_bits { 7118 u8 status[0x8]; 7119 u8 reserved_0[0x18]; 7120 7121 u8 syndrome[0x20]; 7122 7123 u8 reserved_1[0x8]; 7124 u8 mkey_index[0x18]; 7125 7126 u8 reserved_2[0x20]; 7127 }; 7128 7129 struct mlx5_ifc_create_mkey_in_bits { 7130 u8 opcode[0x10]; 7131 u8 reserved_0[0x10]; 7132 7133 u8 reserved_1[0x10]; 7134 u8 op_mod[0x10]; 7135 7136 u8 reserved_2[0x20]; 7137 7138 u8 pg_access[0x1]; 7139 u8 reserved_3[0x1f]; 7140 7141 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7142 7143 u8 reserved_4[0x80]; 7144 7145 u8 translations_octword_actual_size[0x20]; 7146 7147 u8 reserved_5[0x560]; 7148 7149 u8 klm_pas_mtt[0][0x20]; 7150 }; 7151 7152 struct mlx5_ifc_create_flow_table_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_0[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_1[0x8]; 7159 u8 table_id[0x18]; 7160 7161 u8 reserved_2[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_create_flow_table_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 other_vport[0x1]; 7172 u8 reserved_at_41[0xf]; 7173 u8 vport_number[0x10]; 7174 7175 u8 reserved_at_60[0x20]; 7176 7177 u8 table_type[0x8]; 7178 u8 reserved_at_88[0x18]; 7179 7180 u8 reserved_at_a0[0x20]; 7181 7182 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7183 }; 7184 7185 struct mlx5_ifc_create_flow_group_out_bits { 7186 u8 status[0x8]; 7187 u8 reserved_0[0x18]; 7188 7189 u8 syndrome[0x20]; 7190 7191 u8 reserved_1[0x8]; 7192 u8 group_id[0x18]; 7193 7194 u8 reserved_2[0x20]; 7195 }; 7196 7197 enum { 7198 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7199 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7200 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7201 }; 7202 7203 struct mlx5_ifc_create_flow_group_in_bits { 7204 u8 opcode[0x10]; 7205 u8 reserved_0[0x10]; 7206 7207 u8 reserved_1[0x10]; 7208 u8 op_mod[0x10]; 7209 7210 u8 other_vport[0x1]; 7211 u8 reserved_2[0xf]; 7212 u8 vport_number[0x10]; 7213 7214 u8 reserved_3[0x20]; 7215 7216 u8 table_type[0x8]; 7217 u8 reserved_4[0x18]; 7218 7219 u8 reserved_5[0x8]; 7220 u8 table_id[0x18]; 7221 7222 u8 reserved_6[0x20]; 7223 7224 u8 start_flow_index[0x20]; 7225 7226 u8 reserved_7[0x20]; 7227 7228 u8 end_flow_index[0x20]; 7229 7230 u8 reserved_8[0xa0]; 7231 7232 u8 reserved_9[0x18]; 7233 u8 match_criteria_enable[0x8]; 7234 7235 struct mlx5_ifc_fte_match_param_bits match_criteria; 7236 7237 u8 reserved_10[0xe00]; 7238 }; 7239 7240 struct mlx5_ifc_create_eq_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_0[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_1[0x18]; 7247 u8 eq_number[0x8]; 7248 7249 u8 reserved_2[0x20]; 7250 }; 7251 7252 struct mlx5_ifc_create_eq_in_bits { 7253 u8 opcode[0x10]; 7254 u8 reserved_0[0x10]; 7255 7256 u8 reserved_1[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_2[0x40]; 7260 7261 struct mlx5_ifc_eqc_bits eq_context_entry; 7262 7263 u8 reserved_3[0x40]; 7264 7265 u8 event_bitmask[0x40]; 7266 7267 u8 reserved_4[0x580]; 7268 7269 u8 pas[0][0x40]; 7270 }; 7271 7272 struct mlx5_ifc_create_dct_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_0[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_1[0x8]; 7279 u8 dctn[0x18]; 7280 7281 u8 reserved_2[0x20]; 7282 }; 7283 7284 struct mlx5_ifc_create_dct_in_bits { 7285 u8 opcode[0x10]; 7286 u8 reserved_0[0x10]; 7287 7288 u8 reserved_1[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 reserved_2[0x40]; 7292 7293 struct mlx5_ifc_dctc_bits dct_context_entry; 7294 7295 u8 reserved_3[0x180]; 7296 }; 7297 7298 struct mlx5_ifc_create_cq_out_bits { 7299 u8 status[0x8]; 7300 u8 reserved_0[0x18]; 7301 7302 u8 syndrome[0x20]; 7303 7304 u8 reserved_1[0x8]; 7305 u8 cqn[0x18]; 7306 7307 u8 reserved_2[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_create_cq_in_bits { 7311 u8 opcode[0x10]; 7312 u8 reserved_0[0x10]; 7313 7314 u8 reserved_1[0x10]; 7315 u8 op_mod[0x10]; 7316 7317 u8 reserved_2[0x40]; 7318 7319 struct mlx5_ifc_cqc_bits cq_context; 7320 7321 u8 reserved_3[0x600]; 7322 7323 u8 pas[0][0x40]; 7324 }; 7325 7326 struct mlx5_ifc_config_int_moderation_out_bits { 7327 u8 status[0x8]; 7328 u8 reserved_0[0x18]; 7329 7330 u8 syndrome[0x20]; 7331 7332 u8 reserved_1[0x4]; 7333 u8 min_delay[0xc]; 7334 u8 int_vector[0x10]; 7335 7336 u8 reserved_2[0x20]; 7337 }; 7338 7339 enum { 7340 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7341 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7342 }; 7343 7344 struct mlx5_ifc_config_int_moderation_in_bits { 7345 u8 opcode[0x10]; 7346 u8 reserved_0[0x10]; 7347 7348 u8 reserved_1[0x10]; 7349 u8 op_mod[0x10]; 7350 7351 u8 reserved_2[0x4]; 7352 u8 min_delay[0xc]; 7353 u8 int_vector[0x10]; 7354 7355 u8 reserved_3[0x20]; 7356 }; 7357 7358 struct mlx5_ifc_attach_to_mcg_out_bits { 7359 u8 status[0x8]; 7360 u8 reserved_0[0x18]; 7361 7362 u8 syndrome[0x20]; 7363 7364 u8 reserved_1[0x40]; 7365 }; 7366 7367 struct mlx5_ifc_attach_to_mcg_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_0[0x10]; 7370 7371 u8 reserved_1[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 reserved_2[0x8]; 7375 u8 qpn[0x18]; 7376 7377 u8 reserved_3[0x20]; 7378 7379 u8 multicast_gid[16][0x8]; 7380 }; 7381 7382 struct mlx5_ifc_arm_xrc_srq_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_0[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_1[0x40]; 7389 }; 7390 7391 enum { 7392 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7393 }; 7394 7395 struct mlx5_ifc_arm_xrc_srq_in_bits { 7396 u8 opcode[0x10]; 7397 u8 reserved_0[0x10]; 7398 7399 u8 reserved_1[0x10]; 7400 u8 op_mod[0x10]; 7401 7402 u8 reserved_2[0x8]; 7403 u8 xrc_srqn[0x18]; 7404 7405 u8 reserved_3[0x10]; 7406 u8 lwm[0x10]; 7407 }; 7408 7409 struct mlx5_ifc_arm_rq_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_0[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_1[0x40]; 7416 }; 7417 7418 enum { 7419 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7420 }; 7421 7422 struct mlx5_ifc_arm_rq_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_0[0x10]; 7425 7426 u8 reserved_1[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_2[0x8]; 7430 u8 srq_number[0x18]; 7431 7432 u8 reserved_3[0x10]; 7433 u8 lwm[0x10]; 7434 }; 7435 7436 struct mlx5_ifc_arm_dct_out_bits { 7437 u8 status[0x8]; 7438 u8 reserved_0[0x18]; 7439 7440 u8 syndrome[0x20]; 7441 7442 u8 reserved_1[0x40]; 7443 }; 7444 7445 struct mlx5_ifc_arm_dct_in_bits { 7446 u8 opcode[0x10]; 7447 u8 reserved_0[0x10]; 7448 7449 u8 reserved_1[0x10]; 7450 u8 op_mod[0x10]; 7451 7452 u8 reserved_2[0x8]; 7453 u8 dctn[0x18]; 7454 7455 u8 reserved_3[0x20]; 7456 }; 7457 7458 struct mlx5_ifc_alloc_xrcd_out_bits { 7459 u8 status[0x8]; 7460 u8 reserved_0[0x18]; 7461 7462 u8 syndrome[0x20]; 7463 7464 u8 reserved_1[0x8]; 7465 u8 xrcd[0x18]; 7466 7467 u8 reserved_2[0x20]; 7468 }; 7469 7470 struct mlx5_ifc_alloc_xrcd_in_bits { 7471 u8 opcode[0x10]; 7472 u8 reserved_0[0x10]; 7473 7474 u8 reserved_1[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 reserved_2[0x40]; 7478 }; 7479 7480 struct mlx5_ifc_alloc_uar_out_bits { 7481 u8 status[0x8]; 7482 u8 reserved_0[0x18]; 7483 7484 u8 syndrome[0x20]; 7485 7486 u8 reserved_1[0x8]; 7487 u8 uar[0x18]; 7488 7489 u8 reserved_2[0x20]; 7490 }; 7491 7492 struct mlx5_ifc_alloc_uar_in_bits { 7493 u8 opcode[0x10]; 7494 u8 reserved_0[0x10]; 7495 7496 u8 reserved_1[0x10]; 7497 u8 op_mod[0x10]; 7498 7499 u8 reserved_2[0x40]; 7500 }; 7501 7502 struct mlx5_ifc_alloc_transport_domain_out_bits { 7503 u8 status[0x8]; 7504 u8 reserved_0[0x18]; 7505 7506 u8 syndrome[0x20]; 7507 7508 u8 reserved_1[0x8]; 7509 u8 transport_domain[0x18]; 7510 7511 u8 reserved_2[0x20]; 7512 }; 7513 7514 struct mlx5_ifc_alloc_transport_domain_in_bits { 7515 u8 opcode[0x10]; 7516 u8 reserved_0[0x10]; 7517 7518 u8 reserved_1[0x10]; 7519 u8 op_mod[0x10]; 7520 7521 u8 reserved_2[0x40]; 7522 }; 7523 7524 struct mlx5_ifc_alloc_q_counter_out_bits { 7525 u8 status[0x8]; 7526 u8 reserved_0[0x18]; 7527 7528 u8 syndrome[0x20]; 7529 7530 u8 reserved_1[0x18]; 7531 u8 counter_set_id[0x8]; 7532 7533 u8 reserved_2[0x20]; 7534 }; 7535 7536 struct mlx5_ifc_alloc_q_counter_in_bits { 7537 u8 opcode[0x10]; 7538 u8 reserved_0[0x10]; 7539 7540 u8 reserved_1[0x10]; 7541 u8 op_mod[0x10]; 7542 7543 u8 reserved_2[0x40]; 7544 }; 7545 7546 struct mlx5_ifc_alloc_pd_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_0[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_1[0x8]; 7553 u8 pd[0x18]; 7554 7555 u8 reserved_2[0x20]; 7556 }; 7557 7558 struct mlx5_ifc_alloc_pd_in_bits { 7559 u8 opcode[0x10]; 7560 u8 reserved_0[0x10]; 7561 7562 u8 reserved_1[0x10]; 7563 u8 op_mod[0x10]; 7564 7565 u8 reserved_2[0x40]; 7566 }; 7567 7568 struct mlx5_ifc_alloc_flow_counter_out_bits { 7569 u8 status[0x8]; 7570 u8 reserved_0[0x18]; 7571 7572 u8 syndrome[0x20]; 7573 7574 u8 reserved_1[0x10]; 7575 u8 flow_counter_id[0x10]; 7576 7577 u8 reserved_2[0x20]; 7578 }; 7579 7580 struct mlx5_ifc_alloc_flow_counter_in_bits { 7581 u8 opcode[0x10]; 7582 u8 reserved_0[0x10]; 7583 7584 u8 reserved_1[0x10]; 7585 u8 op_mod[0x10]; 7586 7587 u8 reserved_2[0x40]; 7588 }; 7589 7590 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7591 u8 status[0x8]; 7592 u8 reserved_0[0x18]; 7593 7594 u8 syndrome[0x20]; 7595 7596 u8 reserved_1[0x40]; 7597 }; 7598 7599 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7600 u8 opcode[0x10]; 7601 u8 reserved_0[0x10]; 7602 7603 u8 reserved_1[0x10]; 7604 u8 op_mod[0x10]; 7605 7606 u8 reserved_2[0x20]; 7607 7608 u8 reserved_3[0x10]; 7609 u8 vxlan_udp_port[0x10]; 7610 }; 7611 7612 struct mlx5_ifc_activate_tracer_out_bits { 7613 u8 status[0x8]; 7614 u8 reserved_0[0x18]; 7615 7616 u8 syndrome[0x20]; 7617 7618 u8 reserved_1[0x40]; 7619 }; 7620 7621 struct mlx5_ifc_activate_tracer_in_bits { 7622 u8 opcode[0x10]; 7623 u8 reserved_0[0x10]; 7624 7625 u8 reserved_1[0x10]; 7626 u8 op_mod[0x10]; 7627 7628 u8 mkey[0x20]; 7629 7630 u8 reserved_2[0x20]; 7631 }; 7632 7633 struct mlx5_ifc_set_rate_limit_out_bits { 7634 u8 status[0x8]; 7635 u8 reserved_at_8[0x18]; 7636 7637 u8 syndrome[0x20]; 7638 7639 u8 reserved_at_40[0x40]; 7640 }; 7641 7642 struct mlx5_ifc_set_rate_limit_in_bits { 7643 u8 opcode[0x10]; 7644 u8 reserved_at_10[0x10]; 7645 7646 u8 reserved_at_20[0x10]; 7647 u8 op_mod[0x10]; 7648 7649 u8 reserved_at_40[0x10]; 7650 u8 rate_limit_index[0x10]; 7651 7652 u8 reserved_at_60[0x20]; 7653 7654 u8 rate_limit[0x20]; 7655 7656 u8 burst_upper_bound[0x20]; 7657 7658 u8 reserved_at_c0[0x10]; 7659 u8 typical_packet_size[0x10]; 7660 7661 u8 reserved_at_e0[0x120]; 7662 }; 7663 7664 struct mlx5_ifc_access_register_out_bits { 7665 u8 status[0x8]; 7666 u8 reserved_0[0x18]; 7667 7668 u8 syndrome[0x20]; 7669 7670 u8 reserved_1[0x40]; 7671 7672 u8 register_data[0][0x20]; 7673 }; 7674 7675 enum { 7676 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7677 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7678 }; 7679 7680 struct mlx5_ifc_access_register_in_bits { 7681 u8 opcode[0x10]; 7682 u8 reserved_0[0x10]; 7683 7684 u8 reserved_1[0x10]; 7685 u8 op_mod[0x10]; 7686 7687 u8 reserved_2[0x10]; 7688 u8 register_id[0x10]; 7689 7690 u8 argument[0x20]; 7691 7692 u8 register_data[0][0x20]; 7693 }; 7694 7695 struct mlx5_ifc_sltp_reg_bits { 7696 u8 status[0x4]; 7697 u8 version[0x4]; 7698 u8 local_port[0x8]; 7699 u8 pnat[0x2]; 7700 u8 reserved_0[0x2]; 7701 u8 lane[0x4]; 7702 u8 reserved_1[0x8]; 7703 7704 u8 reserved_2[0x20]; 7705 7706 u8 reserved_3[0x7]; 7707 u8 polarity[0x1]; 7708 u8 ob_tap0[0x8]; 7709 u8 ob_tap1[0x8]; 7710 u8 ob_tap2[0x8]; 7711 7712 u8 reserved_4[0xc]; 7713 u8 ob_preemp_mode[0x4]; 7714 u8 ob_reg[0x8]; 7715 u8 ob_bias[0x8]; 7716 7717 u8 reserved_5[0x20]; 7718 }; 7719 7720 struct mlx5_ifc_slrp_reg_bits { 7721 u8 status[0x4]; 7722 u8 version[0x4]; 7723 u8 local_port[0x8]; 7724 u8 pnat[0x2]; 7725 u8 reserved_0[0x2]; 7726 u8 lane[0x4]; 7727 u8 reserved_1[0x8]; 7728 7729 u8 ib_sel[0x2]; 7730 u8 reserved_2[0x11]; 7731 u8 dp_sel[0x1]; 7732 u8 dp90sel[0x4]; 7733 u8 mix90phase[0x8]; 7734 7735 u8 ffe_tap0[0x8]; 7736 u8 ffe_tap1[0x8]; 7737 u8 ffe_tap2[0x8]; 7738 u8 ffe_tap3[0x8]; 7739 7740 u8 ffe_tap4[0x8]; 7741 u8 ffe_tap5[0x8]; 7742 u8 ffe_tap6[0x8]; 7743 u8 ffe_tap7[0x8]; 7744 7745 u8 ffe_tap8[0x8]; 7746 u8 mixerbias_tap_amp[0x8]; 7747 u8 reserved_3[0x7]; 7748 u8 ffe_tap_en[0x9]; 7749 7750 u8 ffe_tap_offset0[0x8]; 7751 u8 ffe_tap_offset1[0x8]; 7752 u8 slicer_offset0[0x10]; 7753 7754 u8 mixer_offset0[0x10]; 7755 u8 mixer_offset1[0x10]; 7756 7757 u8 mixerbgn_inp[0x8]; 7758 u8 mixerbgn_inn[0x8]; 7759 u8 mixerbgn_refp[0x8]; 7760 u8 mixerbgn_refn[0x8]; 7761 7762 u8 sel_slicer_lctrl_h[0x1]; 7763 u8 sel_slicer_lctrl_l[0x1]; 7764 u8 reserved_4[0x1]; 7765 u8 ref_mixer_vreg[0x5]; 7766 u8 slicer_gctrl[0x8]; 7767 u8 lctrl_input[0x8]; 7768 u8 mixer_offset_cm1[0x8]; 7769 7770 u8 common_mode[0x6]; 7771 u8 reserved_5[0x1]; 7772 u8 mixer_offset_cm0[0x9]; 7773 u8 reserved_6[0x7]; 7774 u8 slicer_offset_cm[0x9]; 7775 }; 7776 7777 struct mlx5_ifc_slrg_reg_bits { 7778 u8 status[0x4]; 7779 u8 version[0x4]; 7780 u8 local_port[0x8]; 7781 u8 pnat[0x2]; 7782 u8 reserved_0[0x2]; 7783 u8 lane[0x4]; 7784 u8 reserved_1[0x8]; 7785 7786 u8 time_to_link_up[0x10]; 7787 u8 reserved_2[0xc]; 7788 u8 grade_lane_speed[0x4]; 7789 7790 u8 grade_version[0x8]; 7791 u8 grade[0x18]; 7792 7793 u8 reserved_3[0x4]; 7794 u8 height_grade_type[0x4]; 7795 u8 height_grade[0x18]; 7796 7797 u8 height_dz[0x10]; 7798 u8 height_dv[0x10]; 7799 7800 u8 reserved_4[0x10]; 7801 u8 height_sigma[0x10]; 7802 7803 u8 reserved_5[0x20]; 7804 7805 u8 reserved_6[0x4]; 7806 u8 phase_grade_type[0x4]; 7807 u8 phase_grade[0x18]; 7808 7809 u8 reserved_7[0x8]; 7810 u8 phase_eo_pos[0x8]; 7811 u8 reserved_8[0x8]; 7812 u8 phase_eo_neg[0x8]; 7813 7814 u8 ffe_set_tested[0x10]; 7815 u8 test_errors_per_lane[0x10]; 7816 }; 7817 7818 struct mlx5_ifc_pvlc_reg_bits { 7819 u8 reserved_0[0x8]; 7820 u8 local_port[0x8]; 7821 u8 reserved_1[0x10]; 7822 7823 u8 reserved_2[0x1c]; 7824 u8 vl_hw_cap[0x4]; 7825 7826 u8 reserved_3[0x1c]; 7827 u8 vl_admin[0x4]; 7828 7829 u8 reserved_4[0x1c]; 7830 u8 vl_operational[0x4]; 7831 }; 7832 7833 struct mlx5_ifc_pude_reg_bits { 7834 u8 swid[0x8]; 7835 u8 local_port[0x8]; 7836 u8 reserved_0[0x4]; 7837 u8 admin_status[0x4]; 7838 u8 reserved_1[0x4]; 7839 u8 oper_status[0x4]; 7840 7841 u8 reserved_2[0x60]; 7842 }; 7843 7844 enum { 7845 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7846 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7847 }; 7848 7849 struct mlx5_ifc_ptys_reg_bits { 7850 u8 reserved_0[0x1]; 7851 u8 an_disable_admin[0x1]; 7852 u8 an_disable_cap[0x1]; 7853 u8 reserved_1[0x4]; 7854 u8 force_tx_aba_param[0x1]; 7855 u8 local_port[0x8]; 7856 u8 reserved_2[0xd]; 7857 u8 proto_mask[0x3]; 7858 7859 u8 an_status[0x4]; 7860 u8 reserved_3[0xc]; 7861 u8 data_rate_oper[0x10]; 7862 7863 u8 ext_eth_proto_capability[0x20]; 7864 7865 u8 eth_proto_capability[0x20]; 7866 7867 u8 ib_link_width_capability[0x10]; 7868 u8 ib_proto_capability[0x10]; 7869 7870 u8 ext_eth_proto_admin[0x20]; 7871 7872 u8 eth_proto_admin[0x20]; 7873 7874 u8 ib_link_width_admin[0x10]; 7875 u8 ib_proto_admin[0x10]; 7876 7877 u8 ext_eth_proto_oper[0x20]; 7878 7879 u8 eth_proto_oper[0x20]; 7880 7881 u8 ib_link_width_oper[0x10]; 7882 u8 ib_proto_oper[0x10]; 7883 7884 u8 reserved_4[0x1c]; 7885 u8 connector_type[0x4]; 7886 7887 u8 eth_proto_lp_advertise[0x20]; 7888 7889 u8 reserved_5[0x60]; 7890 }; 7891 7892 struct mlx5_ifc_ptas_reg_bits { 7893 u8 reserved_0[0x20]; 7894 7895 u8 algorithm_options[0x10]; 7896 u8 reserved_1[0x4]; 7897 u8 repetitions_mode[0x4]; 7898 u8 num_of_repetitions[0x8]; 7899 7900 u8 grade_version[0x8]; 7901 u8 height_grade_type[0x4]; 7902 u8 phase_grade_type[0x4]; 7903 u8 height_grade_weight[0x8]; 7904 u8 phase_grade_weight[0x8]; 7905 7906 u8 gisim_measure_bits[0x10]; 7907 u8 adaptive_tap_measure_bits[0x10]; 7908 7909 u8 ber_bath_high_error_threshold[0x10]; 7910 u8 ber_bath_mid_error_threshold[0x10]; 7911 7912 u8 ber_bath_low_error_threshold[0x10]; 7913 u8 one_ratio_high_threshold[0x10]; 7914 7915 u8 one_ratio_high_mid_threshold[0x10]; 7916 u8 one_ratio_low_mid_threshold[0x10]; 7917 7918 u8 one_ratio_low_threshold[0x10]; 7919 u8 ndeo_error_threshold[0x10]; 7920 7921 u8 mixer_offset_step_size[0x10]; 7922 u8 reserved_2[0x8]; 7923 u8 mix90_phase_for_voltage_bath[0x8]; 7924 7925 u8 mixer_offset_start[0x10]; 7926 u8 mixer_offset_end[0x10]; 7927 7928 u8 reserved_3[0x15]; 7929 u8 ber_test_time[0xb]; 7930 }; 7931 7932 struct mlx5_ifc_pspa_reg_bits { 7933 u8 swid[0x8]; 7934 u8 local_port[0x8]; 7935 u8 sub_port[0x8]; 7936 u8 reserved_0[0x8]; 7937 7938 u8 reserved_1[0x20]; 7939 }; 7940 7941 struct mlx5_ifc_ppsc_reg_bits { 7942 u8 reserved_0[0x8]; 7943 u8 local_port[0x8]; 7944 u8 reserved_1[0x10]; 7945 7946 u8 reserved_2[0x60]; 7947 7948 u8 reserved_3[0x1c]; 7949 u8 wrps_admin[0x4]; 7950 7951 u8 reserved_4[0x1c]; 7952 u8 wrps_status[0x4]; 7953 7954 u8 up_th_vld[0x1]; 7955 u8 down_th_vld[0x1]; 7956 u8 reserved_5[0x6]; 7957 u8 up_threshold[0x8]; 7958 u8 reserved_6[0x8]; 7959 u8 down_threshold[0x8]; 7960 7961 u8 reserved_7[0x20]; 7962 7963 u8 reserved_8[0x1c]; 7964 u8 srps_admin[0x4]; 7965 7966 u8 reserved_9[0x60]; 7967 }; 7968 7969 struct mlx5_ifc_pplr_reg_bits { 7970 u8 reserved_0[0x8]; 7971 u8 local_port[0x8]; 7972 u8 reserved_1[0x10]; 7973 7974 u8 reserved_2[0x8]; 7975 u8 lb_cap[0x8]; 7976 u8 reserved_3[0x8]; 7977 u8 lb_en[0x8]; 7978 }; 7979 7980 struct mlx5_ifc_pplm_reg_bits { 7981 u8 reserved_at_0[0x8]; 7982 u8 local_port[0x8]; 7983 u8 reserved_at_10[0x10]; 7984 7985 u8 reserved_at_20[0x20]; 7986 7987 u8 port_profile_mode[0x8]; 7988 u8 static_port_profile[0x8]; 7989 u8 active_port_profile[0x8]; 7990 u8 reserved_at_58[0x8]; 7991 7992 u8 retransmission_active[0x8]; 7993 u8 fec_mode_active[0x18]; 7994 7995 u8 rs_fec_correction_bypass_cap[0x4]; 7996 u8 reserved_at_84[0x8]; 7997 u8 fec_override_cap_56g[0x4]; 7998 u8 fec_override_cap_100g[0x4]; 7999 u8 fec_override_cap_50g[0x4]; 8000 u8 fec_override_cap_25g[0x4]; 8001 u8 fec_override_cap_10g_40g[0x4]; 8002 8003 u8 rs_fec_correction_bypass_admin[0x4]; 8004 u8 reserved_at_a4[0x8]; 8005 u8 fec_override_admin_56g[0x4]; 8006 u8 fec_override_admin_100g[0x4]; 8007 u8 fec_override_admin_50g[0x4]; 8008 u8 fec_override_admin_25g[0x4]; 8009 u8 fec_override_admin_10g_40g[0x4]; 8010 8011 u8 fec_override_cap_400g_8x[0x10]; 8012 u8 fec_override_cap_200g_4x[0x10]; 8013 u8 fec_override_cap_100g_2x[0x10]; 8014 u8 fec_override_cap_50g_1x[0x10]; 8015 8016 u8 fec_override_admin_400g_8x[0x10]; 8017 u8 fec_override_admin_200g_4x[0x10]; 8018 u8 fec_override_admin_100g_2x[0x10]; 8019 u8 fec_override_admin_50g_1x[0x10]; 8020 8021 u8 reserved_at_140[0xC0]; 8022 }; 8023 8024 struct mlx5_ifc_ppll_reg_bits { 8025 u8 num_pll_groups[0x8]; 8026 u8 pll_group[0x8]; 8027 u8 reserved_0[0x4]; 8028 u8 num_plls[0x4]; 8029 u8 reserved_1[0x8]; 8030 8031 u8 reserved_2[0x1f]; 8032 u8 ae[0x1]; 8033 8034 u8 pll_status[4][0x40]; 8035 }; 8036 8037 struct mlx5_ifc_ppad_reg_bits { 8038 u8 reserved_0[0x3]; 8039 u8 single_mac[0x1]; 8040 u8 reserved_1[0x4]; 8041 u8 local_port[0x8]; 8042 u8 mac_47_32[0x10]; 8043 8044 u8 mac_31_0[0x20]; 8045 8046 u8 reserved_2[0x40]; 8047 }; 8048 8049 struct mlx5_ifc_pmtu_reg_bits { 8050 u8 reserved_0[0x8]; 8051 u8 local_port[0x8]; 8052 u8 reserved_1[0x10]; 8053 8054 u8 max_mtu[0x10]; 8055 u8 reserved_2[0x10]; 8056 8057 u8 admin_mtu[0x10]; 8058 u8 reserved_3[0x10]; 8059 8060 u8 oper_mtu[0x10]; 8061 u8 reserved_4[0x10]; 8062 }; 8063 8064 struct mlx5_ifc_pmpr_reg_bits { 8065 u8 reserved_0[0x8]; 8066 u8 module[0x8]; 8067 u8 reserved_1[0x10]; 8068 8069 u8 reserved_2[0x18]; 8070 u8 attenuation_5g[0x8]; 8071 8072 u8 reserved_3[0x18]; 8073 u8 attenuation_7g[0x8]; 8074 8075 u8 reserved_4[0x18]; 8076 u8 attenuation_12g[0x8]; 8077 }; 8078 8079 struct mlx5_ifc_pmpe_reg_bits { 8080 u8 reserved_0[0x8]; 8081 u8 module[0x8]; 8082 u8 reserved_1[0xc]; 8083 u8 module_status[0x4]; 8084 8085 u8 reserved_2[0x14]; 8086 u8 error_type[0x4]; 8087 u8 reserved_3[0x8]; 8088 8089 u8 reserved_4[0x40]; 8090 }; 8091 8092 struct mlx5_ifc_pmpc_reg_bits { 8093 u8 module_state_updated[32][0x8]; 8094 }; 8095 8096 struct mlx5_ifc_pmlpn_reg_bits { 8097 u8 reserved_0[0x4]; 8098 u8 mlpn_status[0x4]; 8099 u8 local_port[0x8]; 8100 u8 reserved_1[0x10]; 8101 8102 u8 e[0x1]; 8103 u8 reserved_2[0x1f]; 8104 }; 8105 8106 struct mlx5_ifc_pmlp_reg_bits { 8107 u8 rxtx[0x1]; 8108 u8 reserved_0[0x7]; 8109 u8 local_port[0x8]; 8110 u8 reserved_1[0x8]; 8111 u8 width[0x8]; 8112 8113 u8 lane0_module_mapping[0x20]; 8114 8115 u8 lane1_module_mapping[0x20]; 8116 8117 u8 lane2_module_mapping[0x20]; 8118 8119 u8 lane3_module_mapping[0x20]; 8120 8121 u8 reserved_2[0x160]; 8122 }; 8123 8124 struct mlx5_ifc_pmaos_reg_bits { 8125 u8 reserved_0[0x8]; 8126 u8 module[0x8]; 8127 u8 reserved_1[0x4]; 8128 u8 admin_status[0x4]; 8129 u8 reserved_2[0x4]; 8130 u8 oper_status[0x4]; 8131 8132 u8 ase[0x1]; 8133 u8 ee[0x1]; 8134 u8 reserved_3[0x12]; 8135 u8 error_type[0x4]; 8136 u8 reserved_4[0x6]; 8137 u8 e[0x2]; 8138 8139 u8 reserved_5[0x40]; 8140 }; 8141 8142 struct mlx5_ifc_plpc_reg_bits { 8143 u8 reserved_0[0x4]; 8144 u8 profile_id[0xc]; 8145 u8 reserved_1[0x4]; 8146 u8 proto_mask[0x4]; 8147 u8 reserved_2[0x8]; 8148 8149 u8 reserved_3[0x10]; 8150 u8 lane_speed[0x10]; 8151 8152 u8 reserved_4[0x17]; 8153 u8 lpbf[0x1]; 8154 u8 fec_mode_policy[0x8]; 8155 8156 u8 retransmission_capability[0x8]; 8157 u8 fec_mode_capability[0x18]; 8158 8159 u8 retransmission_support_admin[0x8]; 8160 u8 fec_mode_support_admin[0x18]; 8161 8162 u8 retransmission_request_admin[0x8]; 8163 u8 fec_mode_request_admin[0x18]; 8164 8165 u8 reserved_5[0x80]; 8166 }; 8167 8168 struct mlx5_ifc_pll_status_data_bits { 8169 u8 reserved_0[0x1]; 8170 u8 lock_cal[0x1]; 8171 u8 lock_status[0x2]; 8172 u8 reserved_1[0x2]; 8173 u8 algo_f_ctrl[0xa]; 8174 u8 analog_algo_num_var[0x6]; 8175 u8 f_ctrl_measure[0xa]; 8176 8177 u8 reserved_2[0x2]; 8178 u8 analog_var[0x6]; 8179 u8 reserved_3[0x2]; 8180 u8 high_var[0x6]; 8181 u8 reserved_4[0x2]; 8182 u8 low_var[0x6]; 8183 u8 reserved_5[0x2]; 8184 u8 mid_val[0x6]; 8185 }; 8186 8187 struct mlx5_ifc_plib_reg_bits { 8188 u8 reserved_0[0x8]; 8189 u8 local_port[0x8]; 8190 u8 reserved_1[0x8]; 8191 u8 ib_port[0x8]; 8192 8193 u8 reserved_2[0x60]; 8194 }; 8195 8196 struct mlx5_ifc_plbf_reg_bits { 8197 u8 reserved_0[0x8]; 8198 u8 local_port[0x8]; 8199 u8 reserved_1[0xd]; 8200 u8 lbf_mode[0x3]; 8201 8202 u8 reserved_2[0x20]; 8203 }; 8204 8205 struct mlx5_ifc_pipg_reg_bits { 8206 u8 reserved_0[0x8]; 8207 u8 local_port[0x8]; 8208 u8 reserved_1[0x10]; 8209 8210 u8 dic[0x1]; 8211 u8 reserved_2[0x19]; 8212 u8 ipg[0x4]; 8213 u8 reserved_3[0x2]; 8214 }; 8215 8216 struct mlx5_ifc_pifr_reg_bits { 8217 u8 reserved_0[0x8]; 8218 u8 local_port[0x8]; 8219 u8 reserved_1[0x10]; 8220 8221 u8 reserved_2[0xe0]; 8222 8223 u8 port_filter[8][0x20]; 8224 8225 u8 port_filter_update_en[8][0x20]; 8226 }; 8227 8228 struct mlx5_ifc_phys_layer_cntrs_bits { 8229 u8 time_since_last_clear_high[0x20]; 8230 8231 u8 time_since_last_clear_low[0x20]; 8232 8233 u8 symbol_errors_high[0x20]; 8234 8235 u8 symbol_errors_low[0x20]; 8236 8237 u8 sync_headers_errors_high[0x20]; 8238 8239 u8 sync_headers_errors_low[0x20]; 8240 8241 u8 edpl_bip_errors_lane0_high[0x20]; 8242 8243 u8 edpl_bip_errors_lane0_low[0x20]; 8244 8245 u8 edpl_bip_errors_lane1_high[0x20]; 8246 8247 u8 edpl_bip_errors_lane1_low[0x20]; 8248 8249 u8 edpl_bip_errors_lane2_high[0x20]; 8250 8251 u8 edpl_bip_errors_lane2_low[0x20]; 8252 8253 u8 edpl_bip_errors_lane3_high[0x20]; 8254 8255 u8 edpl_bip_errors_lane3_low[0x20]; 8256 8257 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8258 8259 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8260 8261 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8262 8263 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8264 8265 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8266 8267 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8268 8269 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8270 8271 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8272 8273 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8274 8275 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8276 8277 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8278 8279 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8280 8281 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8282 8283 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8284 8285 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8286 8287 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8288 8289 u8 rs_fec_corrected_blocks_high[0x20]; 8290 8291 u8 rs_fec_corrected_blocks_low[0x20]; 8292 8293 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8294 8295 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8296 8297 u8 rs_fec_no_errors_blocks_high[0x20]; 8298 8299 u8 rs_fec_no_errors_blocks_low[0x20]; 8300 8301 u8 rs_fec_single_error_blocks_high[0x20]; 8302 8303 u8 rs_fec_single_error_blocks_low[0x20]; 8304 8305 u8 rs_fec_corrected_symbols_total_high[0x20]; 8306 8307 u8 rs_fec_corrected_symbols_total_low[0x20]; 8308 8309 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8310 8311 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8312 8313 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8314 8315 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8316 8317 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8318 8319 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8320 8321 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8322 8323 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8324 8325 u8 link_down_events[0x20]; 8326 8327 u8 successful_recovery_events[0x20]; 8328 8329 u8 reserved_0[0x180]; 8330 }; 8331 8332 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8333 u8 symbol_error_counter[0x10]; 8334 8335 u8 link_error_recovery_counter[0x8]; 8336 8337 u8 link_downed_counter[0x8]; 8338 8339 u8 port_rcv_errors[0x10]; 8340 8341 u8 port_rcv_remote_physical_errors[0x10]; 8342 8343 u8 port_rcv_switch_relay_errors[0x10]; 8344 8345 u8 port_xmit_discards[0x10]; 8346 8347 u8 port_xmit_constraint_errors[0x8]; 8348 8349 u8 port_rcv_constraint_errors[0x8]; 8350 8351 u8 reserved_at_70[0x8]; 8352 8353 u8 link_overrun_errors[0x8]; 8354 8355 u8 reserved_at_80[0x10]; 8356 8357 u8 vl_15_dropped[0x10]; 8358 8359 u8 reserved_at_a0[0xa0]; 8360 }; 8361 8362 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8363 u8 time_since_last_clear_high[0x20]; 8364 8365 u8 time_since_last_clear_low[0x20]; 8366 8367 u8 phy_received_bits_high[0x20]; 8368 8369 u8 phy_received_bits_low[0x20]; 8370 8371 u8 phy_symbol_errors_high[0x20]; 8372 8373 u8 phy_symbol_errors_low[0x20]; 8374 8375 u8 phy_corrected_bits_high[0x20]; 8376 8377 u8 phy_corrected_bits_low[0x20]; 8378 8379 u8 phy_corrected_bits_lane0_high[0x20]; 8380 8381 u8 phy_corrected_bits_lane0_low[0x20]; 8382 8383 u8 phy_corrected_bits_lane1_high[0x20]; 8384 8385 u8 phy_corrected_bits_lane1_low[0x20]; 8386 8387 u8 phy_corrected_bits_lane2_high[0x20]; 8388 8389 u8 phy_corrected_bits_lane2_low[0x20]; 8390 8391 u8 phy_corrected_bits_lane3_high[0x20]; 8392 8393 u8 phy_corrected_bits_lane3_low[0x20]; 8394 8395 u8 reserved_at_200[0x5c0]; 8396 }; 8397 8398 struct mlx5_ifc_infiniband_port_cntrs_bits { 8399 u8 symbol_error_counter[0x10]; 8400 u8 link_error_recovery_counter[0x8]; 8401 u8 link_downed_counter[0x8]; 8402 8403 u8 port_rcv_errors[0x10]; 8404 u8 port_rcv_remote_physical_errors[0x10]; 8405 8406 u8 port_rcv_switch_relay_errors[0x10]; 8407 u8 port_xmit_discards[0x10]; 8408 8409 u8 port_xmit_constraint_errors[0x8]; 8410 u8 port_rcv_constraint_errors[0x8]; 8411 u8 reserved_0[0x8]; 8412 u8 local_link_integrity_errors[0x4]; 8413 u8 excessive_buffer_overrun_errors[0x4]; 8414 8415 u8 reserved_1[0x10]; 8416 u8 vl_15_dropped[0x10]; 8417 8418 u8 port_xmit_data[0x20]; 8419 8420 u8 port_rcv_data[0x20]; 8421 8422 u8 port_xmit_pkts[0x20]; 8423 8424 u8 port_rcv_pkts[0x20]; 8425 8426 u8 port_xmit_wait[0x20]; 8427 8428 u8 reserved_2[0x680]; 8429 }; 8430 8431 struct mlx5_ifc_phrr_reg_bits { 8432 u8 clr[0x1]; 8433 u8 reserved_0[0x7]; 8434 u8 local_port[0x8]; 8435 u8 reserved_1[0x10]; 8436 8437 u8 hist_group[0x8]; 8438 u8 reserved_2[0x10]; 8439 u8 hist_id[0x8]; 8440 8441 u8 reserved_3[0x40]; 8442 8443 u8 time_since_last_clear_high[0x20]; 8444 8445 u8 time_since_last_clear_low[0x20]; 8446 8447 u8 bin[10][0x20]; 8448 }; 8449 8450 struct mlx5_ifc_phbr_for_prio_reg_bits { 8451 u8 reserved_0[0x18]; 8452 u8 prio[0x8]; 8453 }; 8454 8455 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8456 u8 reserved_0[0x18]; 8457 u8 tclass[0x8]; 8458 }; 8459 8460 struct mlx5_ifc_phbr_binding_reg_bits { 8461 u8 opcode[0x4]; 8462 u8 reserved_0[0x4]; 8463 u8 local_port[0x8]; 8464 u8 pnat[0x2]; 8465 u8 reserved_1[0xe]; 8466 8467 u8 hist_group[0x8]; 8468 u8 reserved_2[0x10]; 8469 u8 hist_id[0x8]; 8470 8471 u8 reserved_3[0x10]; 8472 u8 hist_type[0x10]; 8473 8474 u8 hist_parameters[0x20]; 8475 8476 u8 hist_min_value[0x20]; 8477 8478 u8 hist_max_value[0x20]; 8479 8480 u8 sample_time[0x20]; 8481 }; 8482 8483 enum { 8484 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8485 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8486 }; 8487 8488 struct mlx5_ifc_pfcc_reg_bits { 8489 u8 dcbx_operation_type[0x2]; 8490 u8 cap_local_admin[0x1]; 8491 u8 cap_remote_admin[0x1]; 8492 u8 reserved_0[0x4]; 8493 u8 local_port[0x8]; 8494 u8 pnat[0x2]; 8495 u8 reserved_1[0xc]; 8496 u8 shl_cap[0x1]; 8497 u8 shl_opr[0x1]; 8498 8499 u8 ppan[0x4]; 8500 u8 reserved_2[0x4]; 8501 u8 prio_mask_tx[0x8]; 8502 u8 reserved_3[0x8]; 8503 u8 prio_mask_rx[0x8]; 8504 8505 u8 pptx[0x1]; 8506 u8 aptx[0x1]; 8507 u8 reserved_4[0x6]; 8508 u8 pfctx[0x8]; 8509 u8 reserved_5[0x8]; 8510 u8 cbftx[0x8]; 8511 8512 u8 pprx[0x1]; 8513 u8 aprx[0x1]; 8514 u8 reserved_6[0x6]; 8515 u8 pfcrx[0x8]; 8516 u8 reserved_7[0x8]; 8517 u8 cbfrx[0x8]; 8518 8519 u8 device_stall_minor_watermark[0x10]; 8520 u8 device_stall_critical_watermark[0x10]; 8521 8522 u8 reserved_8[0x60]; 8523 }; 8524 8525 struct mlx5_ifc_pelc_reg_bits { 8526 u8 op[0x4]; 8527 u8 reserved_0[0x4]; 8528 u8 local_port[0x8]; 8529 u8 reserved_1[0x10]; 8530 8531 u8 op_admin[0x8]; 8532 u8 op_capability[0x8]; 8533 u8 op_request[0x8]; 8534 u8 op_active[0x8]; 8535 8536 u8 admin[0x40]; 8537 8538 u8 capability[0x40]; 8539 8540 u8 request[0x40]; 8541 8542 u8 active[0x40]; 8543 8544 u8 reserved_2[0x80]; 8545 }; 8546 8547 struct mlx5_ifc_peir_reg_bits { 8548 u8 reserved_0[0x8]; 8549 u8 local_port[0x8]; 8550 u8 reserved_1[0x10]; 8551 8552 u8 reserved_2[0xc]; 8553 u8 error_count[0x4]; 8554 u8 reserved_3[0x10]; 8555 8556 u8 reserved_4[0xc]; 8557 u8 lane[0x4]; 8558 u8 reserved_5[0x8]; 8559 u8 error_type[0x8]; 8560 }; 8561 8562 struct mlx5_ifc_qcam_access_reg_cap_mask { 8563 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8564 u8 qpdpm[0x1]; 8565 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8566 u8 qdpm[0x1]; 8567 u8 qpts[0x1]; 8568 u8 qcap[0x1]; 8569 u8 qcam_access_reg_cap_mask_0[0x1]; 8570 }; 8571 8572 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8573 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8574 u8 qpts_trust_both[0x1]; 8575 }; 8576 8577 struct mlx5_ifc_qcam_reg_bits { 8578 u8 reserved_at_0[0x8]; 8579 u8 feature_group[0x8]; 8580 u8 reserved_at_10[0x8]; 8581 u8 access_reg_group[0x8]; 8582 u8 reserved_at_20[0x20]; 8583 8584 union { 8585 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8586 u8 reserved_at_0[0x80]; 8587 } qos_access_reg_cap_mask; 8588 8589 u8 reserved_at_c0[0x80]; 8590 8591 union { 8592 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8593 u8 reserved_at_0[0x80]; 8594 } qos_feature_cap_mask; 8595 8596 u8 reserved_at_1c0[0x80]; 8597 }; 8598 8599 struct mlx5_ifc_pcam_enhanced_features_bits { 8600 u8 reserved_at_0[0x6d]; 8601 u8 rx_icrc_encapsulated_counter[0x1]; 8602 u8 reserved_at_6e[0x4]; 8603 u8 ptys_extended_ethernet[0x1]; 8604 u8 reserved_at_73[0x3]; 8605 u8 pfcc_mask[0x1]; 8606 u8 reserved_at_77[0x3]; 8607 u8 per_lane_error_counters[0x1]; 8608 u8 rx_buffer_fullness_counters[0x1]; 8609 u8 ptys_connector_type[0x1]; 8610 u8 reserved_at_7d[0x1]; 8611 u8 ppcnt_discard_group[0x1]; 8612 u8 ppcnt_statistical_group[0x1]; 8613 }; 8614 8615 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8616 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8617 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8618 8619 u8 reserved_at_40[0xe]; 8620 u8 pddr[0x1]; 8621 u8 reserved_at_4f[0xd]; 8622 8623 u8 pplm[0x1]; 8624 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8625 8626 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8627 u8 pbmc[0x1]; 8628 u8 pptb[0x1]; 8629 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8630 u8 ppcnt[0x1]; 8631 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8632 }; 8633 8634 struct mlx5_ifc_pcam_reg_bits { 8635 u8 reserved_at_0[0x8]; 8636 u8 feature_group[0x8]; 8637 u8 reserved_at_10[0x8]; 8638 u8 access_reg_group[0x8]; 8639 8640 u8 reserved_at_20[0x20]; 8641 8642 union { 8643 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8644 u8 reserved_at_0[0x80]; 8645 } port_access_reg_cap_mask; 8646 8647 u8 reserved_at_c0[0x80]; 8648 8649 union { 8650 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8651 u8 reserved_at_0[0x80]; 8652 } feature_cap_mask; 8653 8654 u8 reserved_at_1c0[0xc0]; 8655 }; 8656 8657 struct mlx5_ifc_mcam_enhanced_features_bits { 8658 u8 reserved_at_0[0x6e]; 8659 u8 pcie_status_and_power[0x1]; 8660 u8 reserved_at_111[0x10]; 8661 u8 pcie_performance_group[0x1]; 8662 }; 8663 8664 struct mlx5_ifc_mcam_access_reg_bits { 8665 u8 reserved_at_0[0x1c]; 8666 u8 mcda[0x1]; 8667 u8 mcc[0x1]; 8668 u8 mcqi[0x1]; 8669 u8 reserved_at_1f[0x1]; 8670 8671 u8 regs_95_to_64[0x20]; 8672 u8 regs_63_to_32[0x20]; 8673 u8 regs_31_to_0[0x20]; 8674 }; 8675 8676 struct mlx5_ifc_mcam_reg_bits { 8677 u8 reserved_at_0[0x8]; 8678 u8 feature_group[0x8]; 8679 u8 reserved_at_10[0x8]; 8680 u8 access_reg_group[0x8]; 8681 8682 u8 reserved_at_20[0x20]; 8683 8684 union { 8685 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8686 u8 reserved_at_0[0x80]; 8687 } mng_access_reg_cap_mask; 8688 8689 u8 reserved_at_c0[0x80]; 8690 8691 union { 8692 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8693 u8 reserved_at_0[0x80]; 8694 } mng_feature_cap_mask; 8695 8696 u8 reserved_at_1c0[0x80]; 8697 }; 8698 8699 struct mlx5_ifc_pcap_reg_bits { 8700 u8 reserved_0[0x8]; 8701 u8 local_port[0x8]; 8702 u8 reserved_1[0x10]; 8703 8704 u8 port_capability_mask[4][0x20]; 8705 }; 8706 8707 struct mlx5_ifc_pbmc_reg_bits { 8708 u8 reserved_at_0[0x8]; 8709 u8 local_port[0x8]; 8710 u8 reserved_at_10[0x10]; 8711 8712 u8 xoff_timer_value[0x10]; 8713 u8 xoff_refresh[0x10]; 8714 8715 u8 reserved_at_40[0x9]; 8716 u8 fullness_threshold[0x7]; 8717 u8 port_buffer_size[0x10]; 8718 8719 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8720 8721 u8 reserved_at_2e0[0x40]; 8722 }; 8723 8724 struct mlx5_ifc_paos_reg_bits { 8725 u8 swid[0x8]; 8726 u8 local_port[0x8]; 8727 u8 reserved_0[0x4]; 8728 u8 admin_status[0x4]; 8729 u8 reserved_1[0x4]; 8730 u8 oper_status[0x4]; 8731 8732 u8 ase[0x1]; 8733 u8 ee[0x1]; 8734 u8 reserved_2[0x1c]; 8735 u8 e[0x2]; 8736 8737 u8 reserved_3[0x40]; 8738 }; 8739 8740 struct mlx5_ifc_pamp_reg_bits { 8741 u8 reserved_0[0x8]; 8742 u8 opamp_group[0x8]; 8743 u8 reserved_1[0xc]; 8744 u8 opamp_group_type[0x4]; 8745 8746 u8 start_index[0x10]; 8747 u8 reserved_2[0x4]; 8748 u8 num_of_indices[0xc]; 8749 8750 u8 index_data[18][0x10]; 8751 }; 8752 8753 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8754 u8 llr_rx_cells_high[0x20]; 8755 8756 u8 llr_rx_cells_low[0x20]; 8757 8758 u8 llr_rx_error_high[0x20]; 8759 8760 u8 llr_rx_error_low[0x20]; 8761 8762 u8 llr_rx_crc_error_high[0x20]; 8763 8764 u8 llr_rx_crc_error_low[0x20]; 8765 8766 u8 llr_tx_cells_high[0x20]; 8767 8768 u8 llr_tx_cells_low[0x20]; 8769 8770 u8 llr_tx_ret_cells_high[0x20]; 8771 8772 u8 llr_tx_ret_cells_low[0x20]; 8773 8774 u8 llr_tx_ret_events_high[0x20]; 8775 8776 u8 llr_tx_ret_events_low[0x20]; 8777 8778 u8 reserved_0[0x640]; 8779 }; 8780 8781 struct mlx5_ifc_mtmp_reg_bits { 8782 u8 i[0x1]; 8783 u8 reserved_at_1[0x18]; 8784 u8 sensor_index[0x7]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 temperature[0x10]; 8788 8789 u8 mte[0x1]; 8790 u8 mtr[0x1]; 8791 u8 reserved_at_42[0x0e]; 8792 u8 max_temperature[0x10]; 8793 8794 u8 tee[0x2]; 8795 u8 reserved_at_62[0x0e]; 8796 u8 temperature_threshold_hi[0x10]; 8797 8798 u8 reserved_at_80[0x10]; 8799 u8 temperature_threshold_lo[0x10]; 8800 8801 u8 reserved_at_100[0x20]; 8802 8803 u8 sensor_name[0x40]; 8804 }; 8805 8806 struct mlx5_ifc_lane_2_module_mapping_bits { 8807 u8 reserved_0[0x6]; 8808 u8 rx_lane[0x2]; 8809 u8 reserved_1[0x6]; 8810 u8 tx_lane[0x2]; 8811 u8 reserved_2[0x8]; 8812 u8 module[0x8]; 8813 }; 8814 8815 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8816 u8 transmit_queue_high[0x20]; 8817 8818 u8 transmit_queue_low[0x20]; 8819 8820 u8 reserved_0[0x780]; 8821 }; 8822 8823 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8824 u8 no_buffer_discard_uc_high[0x20]; 8825 8826 u8 no_buffer_discard_uc_low[0x20]; 8827 8828 u8 wred_discard_high[0x20]; 8829 8830 u8 wred_discard_low[0x20]; 8831 8832 u8 reserved_0[0x740]; 8833 }; 8834 8835 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8836 u8 rx_octets_high[0x20]; 8837 8838 u8 rx_octets_low[0x20]; 8839 8840 u8 reserved_0[0xc0]; 8841 8842 u8 rx_frames_high[0x20]; 8843 8844 u8 rx_frames_low[0x20]; 8845 8846 u8 tx_octets_high[0x20]; 8847 8848 u8 tx_octets_low[0x20]; 8849 8850 u8 reserved_1[0xc0]; 8851 8852 u8 tx_frames_high[0x20]; 8853 8854 u8 tx_frames_low[0x20]; 8855 8856 u8 rx_pause_high[0x20]; 8857 8858 u8 rx_pause_low[0x20]; 8859 8860 u8 rx_pause_duration_high[0x20]; 8861 8862 u8 rx_pause_duration_low[0x20]; 8863 8864 u8 tx_pause_high[0x20]; 8865 8866 u8 tx_pause_low[0x20]; 8867 8868 u8 tx_pause_duration_high[0x20]; 8869 8870 u8 tx_pause_duration_low[0x20]; 8871 8872 u8 rx_pause_transition_high[0x20]; 8873 8874 u8 rx_pause_transition_low[0x20]; 8875 8876 u8 rx_discards_high[0x20]; 8877 8878 u8 rx_discards_low[0x20]; 8879 8880 u8 device_stall_minor_watermark_cnt_high[0x20]; 8881 8882 u8 device_stall_minor_watermark_cnt_low[0x20]; 8883 8884 u8 device_stall_critical_watermark_cnt_high[0x20]; 8885 8886 u8 device_stall_critical_watermark_cnt_low[0x20]; 8887 8888 u8 reserved_2[0x340]; 8889 }; 8890 8891 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8892 u8 port_transmit_wait_high[0x20]; 8893 8894 u8 port_transmit_wait_low[0x20]; 8895 8896 u8 ecn_marked_high[0x20]; 8897 8898 u8 ecn_marked_low[0x20]; 8899 8900 u8 no_buffer_discard_mc_high[0x20]; 8901 8902 u8 no_buffer_discard_mc_low[0x20]; 8903 8904 u8 rx_ebp_high[0x20]; 8905 8906 u8 rx_ebp_low[0x20]; 8907 8908 u8 tx_ebp_high[0x20]; 8909 8910 u8 tx_ebp_low[0x20]; 8911 8912 u8 rx_buffer_almost_full_high[0x20]; 8913 8914 u8 rx_buffer_almost_full_low[0x20]; 8915 8916 u8 rx_buffer_full_high[0x20]; 8917 8918 u8 rx_buffer_full_low[0x20]; 8919 8920 u8 rx_icrc_encapsulated_high[0x20]; 8921 8922 u8 rx_icrc_encapsulated_low[0x20]; 8923 8924 u8 reserved_0[0x80]; 8925 8926 u8 tx_stats_pkts64octets_high[0x20]; 8927 8928 u8 tx_stats_pkts64octets_low[0x20]; 8929 8930 u8 tx_stats_pkts65to127octets_high[0x20]; 8931 8932 u8 tx_stats_pkts65to127octets_low[0x20]; 8933 8934 u8 tx_stats_pkts128to255octets_high[0x20]; 8935 8936 u8 tx_stats_pkts128to255octets_low[0x20]; 8937 8938 u8 tx_stats_pkts256to511octets_high[0x20]; 8939 8940 u8 tx_stats_pkts256to511octets_low[0x20]; 8941 8942 u8 tx_stats_pkts512to1023octets_high[0x20]; 8943 8944 u8 tx_stats_pkts512to1023octets_low[0x20]; 8945 8946 u8 tx_stats_pkts1024to1518octets_high[0x20]; 8947 8948 u8 tx_stats_pkts1024to1518octets_low[0x20]; 8949 8950 u8 tx_stats_pkts1519to2047octets_high[0x20]; 8951 8952 u8 tx_stats_pkts1519to2047octets_low[0x20]; 8953 8954 u8 tx_stats_pkts2048to4095octets_high[0x20]; 8955 8956 u8 tx_stats_pkts2048to4095octets_low[0x20]; 8957 8958 u8 tx_stats_pkts4096to8191octets_high[0x20]; 8959 8960 u8 tx_stats_pkts4096to8191octets_low[0x20]; 8961 8962 u8 tx_stats_pkts8192to10239octets_high[0x20]; 8963 8964 u8 tx_stats_pkts8192to10239octets_low[0x20]; 8965 8966 u8 reserved_1[0x2C0]; 8967 }; 8968 8969 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8970 u8 a_frames_transmitted_ok_high[0x20]; 8971 8972 u8 a_frames_transmitted_ok_low[0x20]; 8973 8974 u8 a_frames_received_ok_high[0x20]; 8975 8976 u8 a_frames_received_ok_low[0x20]; 8977 8978 u8 a_frame_check_sequence_errors_high[0x20]; 8979 8980 u8 a_frame_check_sequence_errors_low[0x20]; 8981 8982 u8 a_alignment_errors_high[0x20]; 8983 8984 u8 a_alignment_errors_low[0x20]; 8985 8986 u8 a_octets_transmitted_ok_high[0x20]; 8987 8988 u8 a_octets_transmitted_ok_low[0x20]; 8989 8990 u8 a_octets_received_ok_high[0x20]; 8991 8992 u8 a_octets_received_ok_low[0x20]; 8993 8994 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8995 8996 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8997 8998 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8999 9000 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9001 9002 u8 a_multicast_frames_received_ok_high[0x20]; 9003 9004 u8 a_multicast_frames_received_ok_low[0x20]; 9005 9006 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9007 9008 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9009 9010 u8 a_in_range_length_errors_high[0x20]; 9011 9012 u8 a_in_range_length_errors_low[0x20]; 9013 9014 u8 a_out_of_range_length_field_high[0x20]; 9015 9016 u8 a_out_of_range_length_field_low[0x20]; 9017 9018 u8 a_frame_too_long_errors_high[0x20]; 9019 9020 u8 a_frame_too_long_errors_low[0x20]; 9021 9022 u8 a_symbol_error_during_carrier_high[0x20]; 9023 9024 u8 a_symbol_error_during_carrier_low[0x20]; 9025 9026 u8 a_mac_control_frames_transmitted_high[0x20]; 9027 9028 u8 a_mac_control_frames_transmitted_low[0x20]; 9029 9030 u8 a_mac_control_frames_received_high[0x20]; 9031 9032 u8 a_mac_control_frames_received_low[0x20]; 9033 9034 u8 a_unsupported_opcodes_received_high[0x20]; 9035 9036 u8 a_unsupported_opcodes_received_low[0x20]; 9037 9038 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9039 9040 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9041 9042 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9043 9044 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9045 9046 u8 reserved_0[0x300]; 9047 }; 9048 9049 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9050 u8 dot3stats_alignment_errors_high[0x20]; 9051 9052 u8 dot3stats_alignment_errors_low[0x20]; 9053 9054 u8 dot3stats_fcs_errors_high[0x20]; 9055 9056 u8 dot3stats_fcs_errors_low[0x20]; 9057 9058 u8 dot3stats_single_collision_frames_high[0x20]; 9059 9060 u8 dot3stats_single_collision_frames_low[0x20]; 9061 9062 u8 dot3stats_multiple_collision_frames_high[0x20]; 9063 9064 u8 dot3stats_multiple_collision_frames_low[0x20]; 9065 9066 u8 dot3stats_sqe_test_errors_high[0x20]; 9067 9068 u8 dot3stats_sqe_test_errors_low[0x20]; 9069 9070 u8 dot3stats_deferred_transmissions_high[0x20]; 9071 9072 u8 dot3stats_deferred_transmissions_low[0x20]; 9073 9074 u8 dot3stats_late_collisions_high[0x20]; 9075 9076 u8 dot3stats_late_collisions_low[0x20]; 9077 9078 u8 dot3stats_excessive_collisions_high[0x20]; 9079 9080 u8 dot3stats_excessive_collisions_low[0x20]; 9081 9082 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9083 9084 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9085 9086 u8 dot3stats_carrier_sense_errors_high[0x20]; 9087 9088 u8 dot3stats_carrier_sense_errors_low[0x20]; 9089 9090 u8 dot3stats_frame_too_longs_high[0x20]; 9091 9092 u8 dot3stats_frame_too_longs_low[0x20]; 9093 9094 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9095 9096 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9097 9098 u8 dot3stats_symbol_errors_high[0x20]; 9099 9100 u8 dot3stats_symbol_errors_low[0x20]; 9101 9102 u8 dot3control_in_unknown_opcodes_high[0x20]; 9103 9104 u8 dot3control_in_unknown_opcodes_low[0x20]; 9105 9106 u8 dot3in_pause_frames_high[0x20]; 9107 9108 u8 dot3in_pause_frames_low[0x20]; 9109 9110 u8 dot3out_pause_frames_high[0x20]; 9111 9112 u8 dot3out_pause_frames_low[0x20]; 9113 9114 u8 reserved_0[0x3c0]; 9115 }; 9116 9117 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9118 u8 if_in_octets_high[0x20]; 9119 9120 u8 if_in_octets_low[0x20]; 9121 9122 u8 if_in_ucast_pkts_high[0x20]; 9123 9124 u8 if_in_ucast_pkts_low[0x20]; 9125 9126 u8 if_in_discards_high[0x20]; 9127 9128 u8 if_in_discards_low[0x20]; 9129 9130 u8 if_in_errors_high[0x20]; 9131 9132 u8 if_in_errors_low[0x20]; 9133 9134 u8 if_in_unknown_protos_high[0x20]; 9135 9136 u8 if_in_unknown_protos_low[0x20]; 9137 9138 u8 if_out_octets_high[0x20]; 9139 9140 u8 if_out_octets_low[0x20]; 9141 9142 u8 if_out_ucast_pkts_high[0x20]; 9143 9144 u8 if_out_ucast_pkts_low[0x20]; 9145 9146 u8 if_out_discards_high[0x20]; 9147 9148 u8 if_out_discards_low[0x20]; 9149 9150 u8 if_out_errors_high[0x20]; 9151 9152 u8 if_out_errors_low[0x20]; 9153 9154 u8 if_in_multicast_pkts_high[0x20]; 9155 9156 u8 if_in_multicast_pkts_low[0x20]; 9157 9158 u8 if_in_broadcast_pkts_high[0x20]; 9159 9160 u8 if_in_broadcast_pkts_low[0x20]; 9161 9162 u8 if_out_multicast_pkts_high[0x20]; 9163 9164 u8 if_out_multicast_pkts_low[0x20]; 9165 9166 u8 if_out_broadcast_pkts_high[0x20]; 9167 9168 u8 if_out_broadcast_pkts_low[0x20]; 9169 9170 u8 reserved_0[0x480]; 9171 }; 9172 9173 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9174 u8 ether_stats_drop_events_high[0x20]; 9175 9176 u8 ether_stats_drop_events_low[0x20]; 9177 9178 u8 ether_stats_octets_high[0x20]; 9179 9180 u8 ether_stats_octets_low[0x20]; 9181 9182 u8 ether_stats_pkts_high[0x20]; 9183 9184 u8 ether_stats_pkts_low[0x20]; 9185 9186 u8 ether_stats_broadcast_pkts_high[0x20]; 9187 9188 u8 ether_stats_broadcast_pkts_low[0x20]; 9189 9190 u8 ether_stats_multicast_pkts_high[0x20]; 9191 9192 u8 ether_stats_multicast_pkts_low[0x20]; 9193 9194 u8 ether_stats_crc_align_errors_high[0x20]; 9195 9196 u8 ether_stats_crc_align_errors_low[0x20]; 9197 9198 u8 ether_stats_undersize_pkts_high[0x20]; 9199 9200 u8 ether_stats_undersize_pkts_low[0x20]; 9201 9202 u8 ether_stats_oversize_pkts_high[0x20]; 9203 9204 u8 ether_stats_oversize_pkts_low[0x20]; 9205 9206 u8 ether_stats_fragments_high[0x20]; 9207 9208 u8 ether_stats_fragments_low[0x20]; 9209 9210 u8 ether_stats_jabbers_high[0x20]; 9211 9212 u8 ether_stats_jabbers_low[0x20]; 9213 9214 u8 ether_stats_collisions_high[0x20]; 9215 9216 u8 ether_stats_collisions_low[0x20]; 9217 9218 u8 ether_stats_pkts64octets_high[0x20]; 9219 9220 u8 ether_stats_pkts64octets_low[0x20]; 9221 9222 u8 ether_stats_pkts65to127octets_high[0x20]; 9223 9224 u8 ether_stats_pkts65to127octets_low[0x20]; 9225 9226 u8 ether_stats_pkts128to255octets_high[0x20]; 9227 9228 u8 ether_stats_pkts128to255octets_low[0x20]; 9229 9230 u8 ether_stats_pkts256to511octets_high[0x20]; 9231 9232 u8 ether_stats_pkts256to511octets_low[0x20]; 9233 9234 u8 ether_stats_pkts512to1023octets_high[0x20]; 9235 9236 u8 ether_stats_pkts512to1023octets_low[0x20]; 9237 9238 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9239 9240 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9241 9242 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9243 9244 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9245 9246 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9247 9248 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9249 9250 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9251 9252 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9253 9254 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9255 9256 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9257 9258 u8 reserved_0[0x280]; 9259 }; 9260 9261 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9262 u8 symbol_error_counter[0x10]; 9263 u8 link_error_recovery_counter[0x8]; 9264 u8 link_downed_counter[0x8]; 9265 9266 u8 port_rcv_errors[0x10]; 9267 u8 port_rcv_remote_physical_errors[0x10]; 9268 9269 u8 port_rcv_switch_relay_errors[0x10]; 9270 u8 port_xmit_discards[0x10]; 9271 9272 u8 port_xmit_constraint_errors[0x8]; 9273 u8 port_rcv_constraint_errors[0x8]; 9274 u8 reserved_0[0x8]; 9275 u8 local_link_integrity_errors[0x4]; 9276 u8 excessive_buffer_overrun_errors[0x4]; 9277 9278 u8 reserved_1[0x10]; 9279 u8 vl_15_dropped[0x10]; 9280 9281 u8 port_xmit_data[0x20]; 9282 9283 u8 port_rcv_data[0x20]; 9284 9285 u8 port_xmit_pkts[0x20]; 9286 9287 u8 port_rcv_pkts[0x20]; 9288 9289 u8 port_xmit_wait[0x20]; 9290 9291 u8 reserved_2[0x680]; 9292 }; 9293 9294 struct mlx5_ifc_trc_tlb_reg_bits { 9295 u8 reserved_0[0x80]; 9296 9297 u8 tlb_addr[0][0x40]; 9298 }; 9299 9300 struct mlx5_ifc_trc_read_fifo_reg_bits { 9301 u8 reserved_0[0x10]; 9302 u8 requested_event_num[0x10]; 9303 9304 u8 reserved_1[0x20]; 9305 9306 u8 reserved_2[0x10]; 9307 u8 acual_event_num[0x10]; 9308 9309 u8 reserved_3[0x20]; 9310 9311 u8 event[0][0x40]; 9312 }; 9313 9314 struct mlx5_ifc_trc_lock_reg_bits { 9315 u8 reserved_0[0x1f]; 9316 u8 lock[0x1]; 9317 9318 u8 reserved_1[0x60]; 9319 }; 9320 9321 struct mlx5_ifc_trc_filter_reg_bits { 9322 u8 status[0x1]; 9323 u8 reserved_0[0xf]; 9324 u8 filter_index[0x10]; 9325 9326 u8 reserved_1[0x20]; 9327 9328 u8 filter_val[0x20]; 9329 9330 u8 reserved_2[0x1a0]; 9331 }; 9332 9333 struct mlx5_ifc_trc_event_reg_bits { 9334 u8 status[0x1]; 9335 u8 reserved_0[0xf]; 9336 u8 event_index[0x10]; 9337 9338 u8 reserved_1[0x20]; 9339 9340 u8 event_id[0x20]; 9341 9342 u8 event_selector_val[0x10]; 9343 u8 event_selector_size[0x10]; 9344 9345 u8 reserved_2[0x180]; 9346 }; 9347 9348 struct mlx5_ifc_trc_conf_reg_bits { 9349 u8 limit_en[0x1]; 9350 u8 reserved_0[0x3]; 9351 u8 dump_mode[0x4]; 9352 u8 reserved_1[0x15]; 9353 u8 state[0x3]; 9354 9355 u8 reserved_2[0x20]; 9356 9357 u8 limit_event_index[0x20]; 9358 9359 u8 mkey[0x20]; 9360 9361 u8 fifo_ready_ev_num[0x20]; 9362 9363 u8 reserved_3[0x160]; 9364 }; 9365 9366 struct mlx5_ifc_trc_cap_reg_bits { 9367 u8 reserved_0[0x18]; 9368 u8 dump_mode[0x8]; 9369 9370 u8 reserved_1[0x20]; 9371 9372 u8 num_of_events[0x10]; 9373 u8 num_of_filters[0x10]; 9374 9375 u8 fifo_size[0x20]; 9376 9377 u8 tlb_size[0x10]; 9378 u8 event_size[0x10]; 9379 9380 u8 reserved_2[0x160]; 9381 }; 9382 9383 struct mlx5_ifc_set_node_in_bits { 9384 u8 node_description[64][0x8]; 9385 }; 9386 9387 struct mlx5_ifc_register_power_settings_bits { 9388 u8 reserved_0[0x18]; 9389 u8 power_settings_level[0x8]; 9390 9391 u8 reserved_1[0x60]; 9392 }; 9393 9394 struct mlx5_ifc_register_host_endianess_bits { 9395 u8 he[0x1]; 9396 u8 reserved_0[0x1f]; 9397 9398 u8 reserved_1[0x60]; 9399 }; 9400 9401 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9402 u8 physical_address[0x40]; 9403 }; 9404 9405 struct mlx5_ifc_qtct_reg_bits { 9406 u8 operation_type[0x2]; 9407 u8 cap_local_admin[0x1]; 9408 u8 cap_remote_admin[0x1]; 9409 u8 reserved_0[0x4]; 9410 u8 port_number[0x8]; 9411 u8 reserved_1[0xd]; 9412 u8 prio[0x3]; 9413 9414 u8 reserved_2[0x1d]; 9415 u8 tclass[0x3]; 9416 }; 9417 9418 struct mlx5_ifc_qpdp_reg_bits { 9419 u8 reserved_0[0x8]; 9420 u8 port_number[0x8]; 9421 u8 reserved_1[0x10]; 9422 9423 u8 reserved_2[0x1d]; 9424 u8 pprio[0x3]; 9425 }; 9426 9427 struct mlx5_ifc_port_info_ro_fields_param_bits { 9428 u8 reserved_0[0x8]; 9429 u8 port[0x8]; 9430 u8 max_gid[0x10]; 9431 9432 u8 reserved_1[0x20]; 9433 9434 u8 port_guid[0x40]; 9435 }; 9436 9437 struct mlx5_ifc_nvqc_reg_bits { 9438 u8 type[0x20]; 9439 9440 u8 reserved_0[0x18]; 9441 u8 version[0x4]; 9442 u8 reserved_1[0x2]; 9443 u8 support_wr[0x1]; 9444 u8 support_rd[0x1]; 9445 }; 9446 9447 struct mlx5_ifc_nvia_reg_bits { 9448 u8 reserved_0[0x1d]; 9449 u8 target[0x3]; 9450 9451 u8 reserved_1[0x20]; 9452 }; 9453 9454 struct mlx5_ifc_nvdi_reg_bits { 9455 struct mlx5_ifc_config_item_bits configuration_item_header; 9456 }; 9457 9458 struct mlx5_ifc_nvda_reg_bits { 9459 struct mlx5_ifc_config_item_bits configuration_item_header; 9460 9461 u8 configuration_item_data[0x20]; 9462 }; 9463 9464 struct mlx5_ifc_node_info_ro_fields_param_bits { 9465 u8 system_image_guid[0x40]; 9466 9467 u8 reserved_0[0x40]; 9468 9469 u8 node_guid[0x40]; 9470 9471 u8 reserved_1[0x10]; 9472 u8 max_pkey[0x10]; 9473 9474 u8 reserved_2[0x20]; 9475 }; 9476 9477 struct mlx5_ifc_ets_tcn_config_reg_bits { 9478 u8 g[0x1]; 9479 u8 b[0x1]; 9480 u8 r[0x1]; 9481 u8 reserved_0[0x9]; 9482 u8 group[0x4]; 9483 u8 reserved_1[0x9]; 9484 u8 bw_allocation[0x7]; 9485 9486 u8 reserved_2[0xc]; 9487 u8 max_bw_units[0x4]; 9488 u8 reserved_3[0x8]; 9489 u8 max_bw_value[0x8]; 9490 }; 9491 9492 struct mlx5_ifc_ets_global_config_reg_bits { 9493 u8 reserved_0[0x2]; 9494 u8 r[0x1]; 9495 u8 reserved_1[0x1d]; 9496 9497 u8 reserved_2[0xc]; 9498 u8 max_bw_units[0x4]; 9499 u8 reserved_3[0x8]; 9500 u8 max_bw_value[0x8]; 9501 }; 9502 9503 struct mlx5_ifc_qetc_reg_bits { 9504 u8 reserved_at_0[0x8]; 9505 u8 port_number[0x8]; 9506 u8 reserved_at_10[0x30]; 9507 9508 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9509 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9510 }; 9511 9512 struct mlx5_ifc_nodnic_mac_filters_bits { 9513 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9514 9515 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9516 9517 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9518 9519 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9520 9521 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9522 9523 u8 reserved_0[0xc0]; 9524 }; 9525 9526 struct mlx5_ifc_nodnic_gid_filters_bits { 9527 u8 mgid_filter0[16][0x8]; 9528 9529 u8 mgid_filter1[16][0x8]; 9530 9531 u8 mgid_filter2[16][0x8]; 9532 9533 u8 mgid_filter3[16][0x8]; 9534 }; 9535 9536 enum { 9537 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9538 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9539 }; 9540 9541 enum { 9542 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9543 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9544 }; 9545 9546 struct mlx5_ifc_nodnic_config_reg_bits { 9547 u8 no_dram_nic_revision[0x8]; 9548 u8 hardware_format[0x8]; 9549 u8 support_receive_filter[0x1]; 9550 u8 support_promisc_filter[0x1]; 9551 u8 support_promisc_multicast_filter[0x1]; 9552 u8 reserved_0[0x2]; 9553 u8 log_working_buffer_size[0x3]; 9554 u8 log_pkey_table_size[0x4]; 9555 u8 reserved_1[0x3]; 9556 u8 num_ports[0x1]; 9557 9558 u8 reserved_2[0x2]; 9559 u8 log_max_ring_size[0x6]; 9560 u8 reserved_3[0x18]; 9561 9562 u8 lkey[0x20]; 9563 9564 u8 cqe_format[0x4]; 9565 u8 reserved_4[0x1c]; 9566 9567 u8 node_guid[0x40]; 9568 9569 u8 reserved_5[0x740]; 9570 9571 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9572 9573 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9574 }; 9575 9576 struct mlx5_ifc_vlan_layout_bits { 9577 u8 reserved_0[0x14]; 9578 u8 vlan[0xc]; 9579 9580 u8 reserved_1[0x20]; 9581 }; 9582 9583 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9584 u8 reserved_0[0x20]; 9585 9586 u8 mkey[0x20]; 9587 9588 u8 addressh_63_32[0x20]; 9589 9590 u8 addressl_31_0[0x20]; 9591 }; 9592 9593 struct mlx5_ifc_ud_adrs_vector_bits { 9594 u8 dc_key[0x40]; 9595 9596 u8 ext[0x1]; 9597 u8 reserved_0[0x7]; 9598 u8 destination_qp_dct[0x18]; 9599 9600 u8 static_rate[0x4]; 9601 u8 sl_eth_prio[0x4]; 9602 u8 fl[0x1]; 9603 u8 mlid[0x7]; 9604 u8 rlid_udp_sport[0x10]; 9605 9606 u8 reserved_1[0x20]; 9607 9608 u8 rmac_47_16[0x20]; 9609 9610 u8 rmac_15_0[0x10]; 9611 u8 tclass[0x8]; 9612 u8 hop_limit[0x8]; 9613 9614 u8 reserved_2[0x1]; 9615 u8 grh[0x1]; 9616 u8 reserved_3[0x2]; 9617 u8 src_addr_index[0x8]; 9618 u8 flow_label[0x14]; 9619 9620 u8 rgid_rip[16][0x8]; 9621 }; 9622 9623 struct mlx5_ifc_port_module_event_bits { 9624 u8 reserved_0[0x8]; 9625 u8 module[0x8]; 9626 u8 reserved_1[0xc]; 9627 u8 module_status[0x4]; 9628 9629 u8 reserved_2[0x14]; 9630 u8 error_type[0x4]; 9631 u8 reserved_3[0x8]; 9632 9633 u8 reserved_4[0xa0]; 9634 }; 9635 9636 struct mlx5_ifc_icmd_control_bits { 9637 u8 opcode[0x10]; 9638 u8 status[0x8]; 9639 u8 reserved_0[0x7]; 9640 u8 busy[0x1]; 9641 }; 9642 9643 struct mlx5_ifc_eqe_bits { 9644 u8 reserved_0[0x8]; 9645 u8 event_type[0x8]; 9646 u8 reserved_1[0x8]; 9647 u8 event_sub_type[0x8]; 9648 9649 u8 reserved_2[0xe0]; 9650 9651 union mlx5_ifc_event_auto_bits event_data; 9652 9653 u8 reserved_3[0x10]; 9654 u8 signature[0x8]; 9655 u8 reserved_4[0x7]; 9656 u8 owner[0x1]; 9657 }; 9658 9659 enum { 9660 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9661 }; 9662 9663 struct mlx5_ifc_cmd_queue_entry_bits { 9664 u8 type[0x8]; 9665 u8 reserved_0[0x18]; 9666 9667 u8 input_length[0x20]; 9668 9669 u8 input_mailbox_pointer_63_32[0x20]; 9670 9671 u8 input_mailbox_pointer_31_9[0x17]; 9672 u8 reserved_1[0x9]; 9673 9674 u8 command_input_inline_data[16][0x8]; 9675 9676 u8 command_output_inline_data[16][0x8]; 9677 9678 u8 output_mailbox_pointer_63_32[0x20]; 9679 9680 u8 output_mailbox_pointer_31_9[0x17]; 9681 u8 reserved_2[0x9]; 9682 9683 u8 output_length[0x20]; 9684 9685 u8 token[0x8]; 9686 u8 signature[0x8]; 9687 u8 reserved_3[0x8]; 9688 u8 status[0x7]; 9689 u8 ownership[0x1]; 9690 }; 9691 9692 struct mlx5_ifc_cmd_out_bits { 9693 u8 status[0x8]; 9694 u8 reserved_0[0x18]; 9695 9696 u8 syndrome[0x20]; 9697 9698 u8 command_output[0x20]; 9699 }; 9700 9701 struct mlx5_ifc_cmd_in_bits { 9702 u8 opcode[0x10]; 9703 u8 reserved_0[0x10]; 9704 9705 u8 reserved_1[0x10]; 9706 u8 op_mod[0x10]; 9707 9708 u8 command[0][0x20]; 9709 }; 9710 9711 struct mlx5_ifc_cmd_if_box_bits { 9712 u8 mailbox_data[512][0x8]; 9713 9714 u8 reserved_0[0x180]; 9715 9716 u8 next_pointer_63_32[0x20]; 9717 9718 u8 next_pointer_31_10[0x16]; 9719 u8 reserved_1[0xa]; 9720 9721 u8 block_number[0x20]; 9722 9723 u8 reserved_2[0x8]; 9724 u8 token[0x8]; 9725 u8 ctrl_signature[0x8]; 9726 u8 signature[0x8]; 9727 }; 9728 9729 struct mlx5_ifc_mtt_bits { 9730 u8 ptag_63_32[0x20]; 9731 9732 u8 ptag_31_8[0x18]; 9733 u8 reserved_0[0x6]; 9734 u8 wr_en[0x1]; 9735 u8 rd_en[0x1]; 9736 }; 9737 9738 /* Vendor Specific Capabilities, VSC */ 9739 enum { 9740 MLX5_VSC_DOMAIN_ICMD = 0x1, 9741 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9742 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 9743 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9744 }; 9745 9746 struct mlx5_ifc_vendor_specific_cap_bits { 9747 u8 type[0x8]; 9748 u8 length[0x8]; 9749 u8 next_pointer[0x8]; 9750 u8 capability_id[0x8]; 9751 9752 u8 status[0x3]; 9753 u8 reserved_0[0xd]; 9754 u8 space[0x10]; 9755 9756 u8 counter[0x20]; 9757 9758 u8 semaphore[0x20]; 9759 9760 u8 flag[0x1]; 9761 u8 reserved_1[0x1]; 9762 u8 address[0x1e]; 9763 9764 u8 data[0x20]; 9765 }; 9766 9767 struct mlx5_ifc_vsc_space_bits { 9768 u8 status[0x3]; 9769 u8 reserved0[0xd]; 9770 u8 space[0x10]; 9771 }; 9772 9773 struct mlx5_ifc_vsc_addr_bits { 9774 u8 flag[0x1]; 9775 u8 reserved0[0x1]; 9776 u8 address[0x1e]; 9777 }; 9778 9779 enum { 9780 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9781 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9782 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9783 }; 9784 9785 enum { 9786 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9787 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9788 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9789 }; 9790 9791 enum { 9792 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9793 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9794 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9795 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9796 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9797 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9798 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9799 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9800 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9801 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9802 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9803 }; 9804 9805 struct mlx5_ifc_initial_seg_bits { 9806 u8 fw_rev_minor[0x10]; 9807 u8 fw_rev_major[0x10]; 9808 9809 u8 cmd_interface_rev[0x10]; 9810 u8 fw_rev_subminor[0x10]; 9811 9812 u8 reserved_0[0x40]; 9813 9814 u8 cmdq_phy_addr_63_32[0x20]; 9815 9816 u8 cmdq_phy_addr_31_12[0x14]; 9817 u8 reserved_1[0x2]; 9818 u8 nic_interface[0x2]; 9819 u8 log_cmdq_size[0x4]; 9820 u8 log_cmdq_stride[0x4]; 9821 9822 u8 command_doorbell_vector[0x20]; 9823 9824 u8 reserved_2[0xf00]; 9825 9826 u8 initializing[0x1]; 9827 u8 reserved_3[0x4]; 9828 u8 nic_interface_supported[0x3]; 9829 u8 reserved_4[0x18]; 9830 9831 struct mlx5_ifc_health_buffer_bits health_buffer; 9832 9833 u8 no_dram_nic_offset[0x20]; 9834 9835 u8 reserved_5[0x6de0]; 9836 9837 u8 internal_timer_h[0x20]; 9838 9839 u8 internal_timer_l[0x20]; 9840 9841 u8 reserved_6[0x20]; 9842 9843 u8 reserved_7[0x1f]; 9844 u8 clear_int[0x1]; 9845 9846 u8 health_syndrome[0x8]; 9847 u8 health_counter[0x18]; 9848 9849 u8 reserved_8[0x17fc0]; 9850 }; 9851 9852 union mlx5_ifc_icmd_interface_document_bits { 9853 struct mlx5_ifc_fw_version_bits fw_version; 9854 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9855 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9856 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9857 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9858 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9859 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9860 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9861 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9862 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9863 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9864 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9865 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9866 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9867 u8 reserved_0[0x42c0]; 9868 }; 9869 9870 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9871 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9872 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9873 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9874 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9875 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9876 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9877 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9878 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9879 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9880 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9881 u8 reserved_0[0x7c0]; 9882 }; 9883 9884 struct mlx5_ifc_ppcnt_reg_bits { 9885 u8 swid[0x8]; 9886 u8 local_port[0x8]; 9887 u8 pnat[0x2]; 9888 u8 reserved_0[0x8]; 9889 u8 grp[0x6]; 9890 9891 u8 clr[0x1]; 9892 u8 reserved_1[0x1c]; 9893 u8 prio_tc[0x3]; 9894 9895 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9896 }; 9897 9898 struct mlx5_ifc_pcie_lanes_counters_bits { 9899 u8 life_time_counter_high[0x20]; 9900 9901 u8 life_time_counter_low[0x20]; 9902 9903 u8 error_counter_lane0[0x20]; 9904 9905 u8 error_counter_lane1[0x20]; 9906 9907 u8 error_counter_lane2[0x20]; 9908 9909 u8 error_counter_lane3[0x20]; 9910 9911 u8 error_counter_lane4[0x20]; 9912 9913 u8 error_counter_lane5[0x20]; 9914 9915 u8 error_counter_lane6[0x20]; 9916 9917 u8 error_counter_lane7[0x20]; 9918 9919 u8 error_counter_lane8[0x20]; 9920 9921 u8 error_counter_lane9[0x20]; 9922 9923 u8 error_counter_lane10[0x20]; 9924 9925 u8 error_counter_lane11[0x20]; 9926 9927 u8 error_counter_lane12[0x20]; 9928 9929 u8 error_counter_lane13[0x20]; 9930 9931 u8 error_counter_lane14[0x20]; 9932 9933 u8 error_counter_lane15[0x20]; 9934 9935 u8 reserved_at_240[0x580]; 9936 }; 9937 9938 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 9939 u8 reserved_at_0[0x40]; 9940 9941 u8 error_counter_lane0[0x20]; 9942 9943 u8 error_counter_lane1[0x20]; 9944 9945 u8 error_counter_lane2[0x20]; 9946 9947 u8 error_counter_lane3[0x20]; 9948 9949 u8 error_counter_lane4[0x20]; 9950 9951 u8 error_counter_lane5[0x20]; 9952 9953 u8 error_counter_lane6[0x20]; 9954 9955 u8 error_counter_lane7[0x20]; 9956 9957 u8 error_counter_lane8[0x20]; 9958 9959 u8 error_counter_lane9[0x20]; 9960 9961 u8 error_counter_lane10[0x20]; 9962 9963 u8 error_counter_lane11[0x20]; 9964 9965 u8 error_counter_lane12[0x20]; 9966 9967 u8 error_counter_lane13[0x20]; 9968 9969 u8 error_counter_lane14[0x20]; 9970 9971 u8 error_counter_lane15[0x20]; 9972 9973 u8 reserved_at_240[0x580]; 9974 }; 9975 9976 struct mlx5_ifc_pcie_perf_counters_bits { 9977 u8 life_time_counter_high[0x20]; 9978 9979 u8 life_time_counter_low[0x20]; 9980 9981 u8 rx_errors[0x20]; 9982 9983 u8 tx_errors[0x20]; 9984 9985 u8 l0_to_recovery_eieos[0x20]; 9986 9987 u8 l0_to_recovery_ts[0x20]; 9988 9989 u8 l0_to_recovery_framing[0x20]; 9990 9991 u8 l0_to_recovery_retrain[0x20]; 9992 9993 u8 crc_error_dllp[0x20]; 9994 9995 u8 crc_error_tlp[0x20]; 9996 9997 u8 tx_overflow_buffer_pkt[0x40]; 9998 9999 u8 outbound_stalled_reads[0x20]; 10000 10001 u8 outbound_stalled_writes[0x20]; 10002 10003 u8 outbound_stalled_reads_events[0x20]; 10004 10005 u8 outbound_stalled_writes_events[0x20]; 10006 10007 u8 tx_overflow_buffer_marked_pkt[0x40]; 10008 10009 u8 reserved_at_240[0x580]; 10010 }; 10011 10012 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10013 u8 reserved_at_0[0x40]; 10014 10015 u8 rx_errors[0x20]; 10016 10017 u8 tx_errors[0x20]; 10018 10019 u8 reserved_at_80[0xc0]; 10020 10021 u8 tx_overflow_buffer_pkt[0x40]; 10022 10023 u8 outbound_stalled_reads[0x20]; 10024 10025 u8 outbound_stalled_writes[0x20]; 10026 10027 u8 outbound_stalled_reads_events[0x20]; 10028 10029 u8 outbound_stalled_writes_events[0x20]; 10030 10031 u8 tx_overflow_buffer_marked_pkt[0x40]; 10032 10033 u8 reserved_at_240[0x580]; 10034 }; 10035 10036 struct mlx5_ifc_pcie_timers_states_bits { 10037 u8 life_time_counter_high[0x20]; 10038 10039 u8 life_time_counter_low[0x20]; 10040 10041 u8 time_to_boot_image_start[0x20]; 10042 10043 u8 time_to_link_image[0x20]; 10044 10045 u8 calibration_time[0x20]; 10046 10047 u8 time_to_first_perst[0x20]; 10048 10049 u8 time_to_detect_state[0x20]; 10050 10051 u8 time_to_l0[0x20]; 10052 10053 u8 time_to_crs_en[0x20]; 10054 10055 u8 time_to_plastic_image_start[0x20]; 10056 10057 u8 time_to_iron_image_start[0x20]; 10058 10059 u8 perst_handler[0x20]; 10060 10061 u8 times_in_l1[0x20]; 10062 10063 u8 times_in_l23[0x20]; 10064 10065 u8 dl_down[0x20]; 10066 10067 u8 config_cycle1usec[0x20]; 10068 10069 u8 config_cycle2to7usec[0x20]; 10070 10071 u8 config_cycle8to15usec[0x20]; 10072 10073 u8 config_cycle16to63usec[0x20]; 10074 10075 u8 config_cycle64usec[0x20]; 10076 10077 u8 correctable_err_msg_sent[0x20]; 10078 10079 u8 non_fatal_err_msg_sent[0x20]; 10080 10081 u8 fatal_err_msg_sent[0x20]; 10082 10083 u8 reserved_at_2e0[0x4e0]; 10084 }; 10085 10086 struct mlx5_ifc_pcie_timers_states_ext_bits { 10087 u8 reserved_at_0[0x40]; 10088 10089 u8 time_to_boot_image_start[0x20]; 10090 10091 u8 time_to_link_image[0x20]; 10092 10093 u8 calibration_time[0x20]; 10094 10095 u8 time_to_first_perst[0x20]; 10096 10097 u8 time_to_detect_state[0x20]; 10098 10099 u8 time_to_l0[0x20]; 10100 10101 u8 time_to_crs_en[0x20]; 10102 10103 u8 time_to_plastic_image_start[0x20]; 10104 10105 u8 time_to_iron_image_start[0x20]; 10106 10107 u8 perst_handler[0x20]; 10108 10109 u8 times_in_l1[0x20]; 10110 10111 u8 times_in_l23[0x20]; 10112 10113 u8 dl_down[0x20]; 10114 10115 u8 config_cycle1usec[0x20]; 10116 10117 u8 config_cycle2to7usec[0x20]; 10118 10119 u8 config_cycle8to15usec[0x20]; 10120 10121 u8 config_cycle16to63usec[0x20]; 10122 10123 u8 config_cycle64usec[0x20]; 10124 10125 u8 correctable_err_msg_sent[0x20]; 10126 10127 u8 non_fatal_err_msg_sent[0x20]; 10128 10129 u8 fatal_err_msg_sent[0x20]; 10130 10131 u8 reserved_at_2e0[0x4e0]; 10132 }; 10133 10134 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10135 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10136 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10137 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10138 u8 reserved_at_0[0x7c0]; 10139 }; 10140 10141 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10142 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10143 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10144 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10145 u8 reserved_at_0[0x7c0]; 10146 }; 10147 10148 struct mlx5_ifc_mpcnt_reg_bits { 10149 u8 reserved_at_0[0x2]; 10150 u8 depth[0x6]; 10151 u8 pcie_index[0x8]; 10152 u8 node[0x8]; 10153 u8 reserved_at_18[0x2]; 10154 u8 grp[0x6]; 10155 10156 u8 clr[0x1]; 10157 u8 reserved_at_21[0x1f]; 10158 10159 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10160 }; 10161 10162 struct mlx5_ifc_mpcnt_reg_ext_bits { 10163 u8 reserved_at_0[0x2]; 10164 u8 depth[0x6]; 10165 u8 pcie_index[0x8]; 10166 u8 node[0x8]; 10167 u8 reserved_at_18[0x2]; 10168 u8 grp[0x6]; 10169 10170 u8 clr[0x1]; 10171 u8 reserved_at_21[0x1f]; 10172 10173 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10174 }; 10175 10176 struct mlx5_ifc_monitor_opcodes_layout_bits { 10177 u8 reserved_at_0[0x10]; 10178 u8 monitor_opcode[0x10]; 10179 }; 10180 10181 union mlx5_ifc_pddr_status_opcode_bits { 10182 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10183 u8 reserved_at_0[0x20]; 10184 }; 10185 10186 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10187 u8 reserved_at_0[0x10]; 10188 u8 group_opcode[0x10]; 10189 10190 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10191 10192 u8 user_feedback_data[0x10]; 10193 u8 user_feedback_index[0x10]; 10194 10195 u8 status_message[0x760]; 10196 }; 10197 10198 union mlx5_ifc_pddr_page_data_bits { 10199 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10200 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10201 u8 reserved_at_0[0x7c0]; 10202 }; 10203 10204 struct mlx5_ifc_pddr_reg_bits { 10205 u8 reserved_at_0[0x8]; 10206 u8 local_port[0x8]; 10207 u8 pnat[0x2]; 10208 u8 reserved_at_12[0xe]; 10209 10210 u8 reserved_at_20[0x18]; 10211 u8 page_select[0x8]; 10212 10213 union mlx5_ifc_pddr_page_data_bits page_data; 10214 }; 10215 10216 enum { 10217 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10218 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10219 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10220 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10221 }; 10222 10223 struct mlx5_ifc_mpein_reg_bits { 10224 u8 reserved_at_0[0x2]; 10225 u8 depth[0x6]; 10226 u8 pcie_index[0x8]; 10227 u8 node[0x8]; 10228 u8 reserved_at_18[0x8]; 10229 10230 u8 capability_mask[0x20]; 10231 10232 u8 reserved_at_40[0x8]; 10233 u8 link_width_enabled[0x8]; 10234 u8 link_speed_enabled[0x10]; 10235 10236 u8 lane0_physical_position[0x8]; 10237 u8 link_width_active[0x8]; 10238 u8 link_speed_active[0x10]; 10239 10240 u8 num_of_pfs[0x10]; 10241 u8 num_of_vfs[0x10]; 10242 10243 u8 bdf0[0x10]; 10244 u8 reserved_at_b0[0x10]; 10245 10246 u8 max_read_request_size[0x4]; 10247 u8 max_payload_size[0x4]; 10248 u8 reserved_at_c8[0x5]; 10249 u8 pwr_status[0x3]; 10250 u8 port_type[0x4]; 10251 u8 reserved_at_d4[0xb]; 10252 u8 lane_reversal[0x1]; 10253 10254 u8 reserved_at_e0[0x14]; 10255 u8 pci_power[0xc]; 10256 10257 u8 reserved_at_100[0x20]; 10258 10259 u8 device_status[0x10]; 10260 u8 port_state[0x8]; 10261 u8 reserved_at_138[0x8]; 10262 10263 u8 reserved_at_140[0x10]; 10264 u8 receiver_detect_result[0x10]; 10265 10266 u8 reserved_at_160[0x20]; 10267 }; 10268 10269 struct mlx5_ifc_mpein_reg_ext_bits { 10270 u8 reserved_at_0[0x2]; 10271 u8 depth[0x6]; 10272 u8 pcie_index[0x8]; 10273 u8 node[0x8]; 10274 u8 reserved_at_18[0x8]; 10275 10276 u8 reserved_at_20[0x20]; 10277 10278 u8 reserved_at_40[0x8]; 10279 u8 link_width_enabled[0x8]; 10280 u8 link_speed_enabled[0x10]; 10281 10282 u8 lane0_physical_position[0x8]; 10283 u8 link_width_active[0x8]; 10284 u8 link_speed_active[0x10]; 10285 10286 u8 num_of_pfs[0x10]; 10287 u8 num_of_vfs[0x10]; 10288 10289 u8 bdf0[0x10]; 10290 u8 reserved_at_b0[0x10]; 10291 10292 u8 max_read_request_size[0x4]; 10293 u8 max_payload_size[0x4]; 10294 u8 reserved_at_c8[0x5]; 10295 u8 pwr_status[0x3]; 10296 u8 port_type[0x4]; 10297 u8 reserved_at_d4[0xb]; 10298 u8 lane_reversal[0x1]; 10299 }; 10300 10301 struct mlx5_ifc_mcqi_cap_bits { 10302 u8 supported_info_bitmask[0x20]; 10303 10304 u8 component_size[0x20]; 10305 10306 u8 max_component_size[0x20]; 10307 10308 u8 log_mcda_word_size[0x4]; 10309 u8 reserved_at_64[0xc]; 10310 u8 mcda_max_write_size[0x10]; 10311 10312 u8 rd_en[0x1]; 10313 u8 reserved_at_81[0x1]; 10314 u8 match_chip_id[0x1]; 10315 u8 match_psid[0x1]; 10316 u8 check_user_timestamp[0x1]; 10317 u8 match_base_guid_mac[0x1]; 10318 u8 reserved_at_86[0x1a]; 10319 }; 10320 10321 struct mlx5_ifc_mcqi_reg_bits { 10322 u8 read_pending_component[0x1]; 10323 u8 reserved_at_1[0xf]; 10324 u8 component_index[0x10]; 10325 10326 u8 reserved_at_20[0x20]; 10327 10328 u8 reserved_at_40[0x1b]; 10329 u8 info_type[0x5]; 10330 10331 u8 info_size[0x20]; 10332 10333 u8 offset[0x20]; 10334 10335 u8 reserved_at_a0[0x10]; 10336 u8 data_size[0x10]; 10337 10338 u8 data[0][0x20]; 10339 }; 10340 10341 struct mlx5_ifc_mcc_reg_bits { 10342 u8 reserved_at_0[0x4]; 10343 u8 time_elapsed_since_last_cmd[0xc]; 10344 u8 reserved_at_10[0x8]; 10345 u8 instruction[0x8]; 10346 10347 u8 reserved_at_20[0x10]; 10348 u8 component_index[0x10]; 10349 10350 u8 reserved_at_40[0x8]; 10351 u8 update_handle[0x18]; 10352 10353 u8 handle_owner_type[0x4]; 10354 u8 handle_owner_host_id[0x4]; 10355 u8 reserved_at_68[0x1]; 10356 u8 control_progress[0x7]; 10357 u8 error_code[0x8]; 10358 u8 reserved_at_78[0x4]; 10359 u8 control_state[0x4]; 10360 10361 u8 component_size[0x20]; 10362 10363 u8 reserved_at_a0[0x60]; 10364 }; 10365 10366 struct mlx5_ifc_mcda_reg_bits { 10367 u8 reserved_at_0[0x8]; 10368 u8 update_handle[0x18]; 10369 10370 u8 offset[0x20]; 10371 10372 u8 reserved_at_40[0x10]; 10373 u8 size[0x10]; 10374 10375 u8 reserved_at_60[0x20]; 10376 10377 u8 data[0][0x20]; 10378 }; 10379 10380 union mlx5_ifc_ports_control_registers_document_bits { 10381 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10382 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10383 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10384 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10385 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10386 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10387 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10388 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10389 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10390 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10391 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10392 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10393 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10394 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10395 struct mlx5_ifc_paos_reg_bits paos_reg; 10396 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10397 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10398 struct mlx5_ifc_peir_reg_bits peir_reg; 10399 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10400 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10401 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10402 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10403 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10404 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10405 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10406 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10407 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10408 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10409 struct mlx5_ifc_plib_reg_bits plib_reg; 10410 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10411 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10412 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10413 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10414 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10415 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10416 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10417 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10418 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10419 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10420 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10421 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10422 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10423 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10424 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10425 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10426 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10427 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10428 struct mlx5_ifc_pude_reg_bits pude_reg; 10429 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10430 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10431 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10432 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10433 u8 reserved_0[0x7880]; 10434 }; 10435 10436 union mlx5_ifc_debug_enhancements_document_bits { 10437 struct mlx5_ifc_health_buffer_bits health_buffer; 10438 u8 reserved_0[0x200]; 10439 }; 10440 10441 union mlx5_ifc_no_dram_nic_document_bits { 10442 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10443 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10444 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10445 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10446 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10447 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10448 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10449 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10450 u8 reserved_0[0x3160]; 10451 }; 10452 10453 union mlx5_ifc_uplink_pci_interface_document_bits { 10454 struct mlx5_ifc_initial_seg_bits initial_seg; 10455 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10456 u8 reserved_0[0x20120]; 10457 }; 10458 10459 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10460 u8 e[0x1]; 10461 u8 reserved_at_01[0x0b]; 10462 u8 prio[0x04]; 10463 }; 10464 10465 struct mlx5_ifc_qpdpm_reg_bits { 10466 u8 reserved_at_0[0x8]; 10467 u8 local_port[0x8]; 10468 u8 reserved_at_10[0x10]; 10469 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10470 }; 10471 10472 struct mlx5_ifc_qpts_reg_bits { 10473 u8 reserved_at_0[0x8]; 10474 u8 local_port[0x8]; 10475 u8 reserved_at_10[0x2d]; 10476 u8 trust_state[0x3]; 10477 }; 10478 10479 struct mlx5_ifc_mfrl_reg_bits { 10480 u8 reserved_at_0[0x38]; 10481 u8 reset_level[0x8]; 10482 }; 10483 10484 enum { 10485 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10486 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10487 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10488 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10489 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10490 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10491 MLX5_MAX_TEMPERATURE = 16, 10492 }; 10493 10494 struct mlx5_ifc_mtbr_temp_record_bits { 10495 u8 max_temperature[0x10]; 10496 u8 temperature[0x10]; 10497 }; 10498 10499 struct mlx5_ifc_mtbr_reg_bits { 10500 u8 reserved_at_0[0x14]; 10501 u8 base_sensor_index[0xc]; 10502 10503 u8 reserved_at_20[0x18]; 10504 u8 num_rec[0x8]; 10505 10506 u8 reserved_at_40[0x40]; 10507 10508 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10509 }; 10510 10511 struct mlx5_ifc_mtbr_reg_ext_bits { 10512 u8 reserved_at_0[0x14]; 10513 u8 base_sensor_index[0xc]; 10514 10515 u8 reserved_at_20[0x18]; 10516 u8 num_rec[0x8]; 10517 10518 u8 reserved_at_40[0x40]; 10519 10520 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10521 }; 10522 10523 struct mlx5_ifc_mtcap_bits { 10524 u8 reserved_at_0[0x19]; 10525 u8 sensor_count[0x7]; 10526 10527 u8 reserved_at_20[0x19]; 10528 u8 internal_sensor_count[0x7]; 10529 10530 u8 sensor_map[0x40]; 10531 }; 10532 10533 struct mlx5_ifc_mtcap_ext_bits { 10534 u8 reserved_at_0[0x19]; 10535 u8 sensor_count[0x7]; 10536 10537 u8 reserved_at_20[0x20]; 10538 10539 u8 sensor_map[0x40]; 10540 }; 10541 10542 struct mlx5_ifc_mtecr_bits { 10543 u8 reserved_at_0[0x4]; 10544 u8 last_sensor[0xc]; 10545 u8 reserved_at_10[0x4]; 10546 u8 sensor_count[0xc]; 10547 10548 u8 reserved_at_20[0x19]; 10549 u8 internal_sensor_count[0x7]; 10550 10551 u8 sensor_map_0[0x20]; 10552 10553 u8 reserved_at_60[0x2a0]; 10554 }; 10555 10556 struct mlx5_ifc_mtecr_ext_bits { 10557 u8 reserved_at_0[0x4]; 10558 u8 last_sensor[0xc]; 10559 u8 reserved_at_10[0x4]; 10560 u8 sensor_count[0xc]; 10561 10562 u8 reserved_at_20[0x20]; 10563 10564 u8 sensor_map_0[0x20]; 10565 10566 u8 reserved_at_60[0x2a0]; 10567 }; 10568 10569 struct mlx5_ifc_mtewe_bits { 10570 u8 reserved_at_0[0x4]; 10571 u8 last_sensor[0xc]; 10572 u8 reserved_at_10[0x4]; 10573 u8 sensor_count[0xc]; 10574 10575 u8 sensor_warning_0[0x20]; 10576 10577 u8 reserved_at_40[0x2a0]; 10578 }; 10579 10580 struct mlx5_ifc_mtewe_ext_bits { 10581 u8 reserved_at_0[0x4]; 10582 u8 last_sensor[0xc]; 10583 u8 reserved_at_10[0x4]; 10584 u8 sensor_count[0xc]; 10585 10586 u8 sensor_warning_0[0x20]; 10587 10588 u8 reserved_at_40[0x2a0]; 10589 }; 10590 10591 struct mlx5_ifc_mtmp_bits { 10592 u8 reserved_at_0[0x14]; 10593 u8 sensor_index[0xc]; 10594 10595 u8 reserved_at_20[0x10]; 10596 u8 temperature[0x10]; 10597 10598 u8 mte[0x1]; 10599 u8 mtr[0x1]; 10600 u8 reserved_at_42[0xe]; 10601 u8 max_temperature[0x10]; 10602 10603 u8 tee[0x2]; 10604 u8 reserved_at_62[0xe]; 10605 u8 temperature_threshold_hi[0x10]; 10606 10607 u8 reserved_at_80[0x10]; 10608 u8 temperature_threshold_lo[0x10]; 10609 10610 u8 reserved_at_a0[0x20]; 10611 10612 u8 sensor_name_hi[0x20]; 10613 10614 u8 sensor_name_lo[0x20]; 10615 }; 10616 10617 struct mlx5_ifc_mtmp_ext_bits { 10618 u8 reserved_at_0[0x14]; 10619 u8 sensor_index[0xc]; 10620 10621 u8 reserved_at_20[0x10]; 10622 u8 temperature[0x10]; 10623 10624 u8 mte[0x1]; 10625 u8 mtr[0x1]; 10626 u8 reserved_at_42[0xe]; 10627 u8 max_temperature[0x10]; 10628 10629 u8 tee[0x2]; 10630 u8 reserved_at_62[0xe]; 10631 u8 temperature_threshold_hi[0x10]; 10632 10633 u8 reserved_at_80[0x10]; 10634 u8 temperature_threshold_lo[0x10]; 10635 10636 u8 reserved_at_a0[0x20]; 10637 10638 u8 sensor_name_hi[0x20]; 10639 10640 u8 sensor_name_lo[0x20]; 10641 }; 10642 10643 #endif /* MLX5_IFC_H */ 10644