Searched refs:buildXor (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2150 B.buildSub(Dst, B.buildXor(S64, B.buildMerge(S64, {Lo, Hi}), Sign), Sign); in legalizeFPTOI()
3135 LHS = B.buildXor(Ty, LHS, LHSign).getReg(0); in legalizeSignedDIV_REM()
3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM()
3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
3168 auto SignXor = B.buildXor(Ty, TmpDivReg, Sign).getReg(0); in legalizeSignedDIV_REM()
3174 auto SignXor = B.buildXor(Ty, TmpRemReg, Sign).getReg(0); in legalizeSignedDIV_REM()
3461 Scale = B.buildXor(S1, CmpNum, CmpDen).getReg(0); in legalizeFDIV64()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 1143 auto Xor = MIRBuilder.buildXor(NarrowTy, LHS, RHS).getReg(0); in narrowScalar()
1153 auto Xor = MIRBuilder.buildXor(LeftoverTy, LHS, RHS).getReg(0); in narrowScalar()
3214 MIRBuilder.buildXor(Res, SubByReg, SignMask); in lower()
5726 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); in lowerBitCount()
6119 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); in lowerSITOFP()
6164 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); in lowerFPTOUI()
6228 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); in lowerFPTOSI()
6902 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); in lowerSADDO_SSUBO()
7277 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); in lowerAbsToAddXor()
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| D | CombinerHelper.cpp | 1081 auto Xor = Builder.buildXor(Ty, BrCond->getOperand(0), True); in applyOptBrCondByInvertingCond()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 1527 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor() function
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