Searched refs:buildUndef (Results 1 – 11 of 11) sorted by relevance
571 buildUndef(ResIn); in buildSequence()582 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder662 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
284 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()329 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()846 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()857 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()1392 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()1402 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()1515 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()1560 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); in widenWithUnmerge()3498 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); in fewerElementsVectorImplicitDef()4014 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()[all …]
272 Register Undef = B.buildUndef(PartLLT).getReg(0); in mergeVectorRegsToResultRegs()500 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
204 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()237 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()318 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()2821 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()2895 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2133 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()2578 MIRBuilder.buildUndef(Undef); in translateLandingPad()2934 EntryBuilder->buildUndef(Reg); in translate()
2203 B.buildUndef(Dst); in legalizeExtractVectorElt()2236 B.buildUndef(Dst); in legalizeInsertVectorElt()2376 B.buildUndef(DstReg); in legalizeGlobalValue()3751 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()3761 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()3772 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()4188 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()4221 auto Undef = B.buildUndef(S32); in convertImageAddrToPacked()4289 B.buildUndef(MI.getOperand(0)); in legalizeImageIntrinsic()4594 Register Undef = B.buildUndef(Ty).getReg(0); in legalizeImageIntrinsic()
646 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
745 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop()1195 auto Undef = B.buildUndef(LoadTy); in applyMappingLoad()1945 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
400 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()412 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
711 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
894 MachineInstrBuilder buildUndef(const DstOp &Res);