1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/12/sys/arm/nvidia/tegra_xhci.c 338318 2018-08-25 19:38:08Z alc $");
29
30 /*
31 * XHCI driver for Tegra SoCs.
32 */
33 #include "opt_bus.h"
34 #include "opt_platform.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/bus.h>
42 #include <sys/clock.h>
43 #include <sys/condvar.h>
44 #include <sys/firmware.h>
45 #include <sys/rman.h>
46
47 #include <vm/vm.h>
48 #include <vm/vm_extern.h>
49 #include <vm/vm_kern.h>
50 #include <vm/pmap.h>
51
52 #include <machine/bus.h>
53 #include <machine/resource.h>
54
55
56 #include <dev/extres/clk/clk.h>
57 #include <dev/extres/hwreset/hwreset.h>
58 #include <dev/extres/phy/phy.h>
59 #include <dev/extres/regulator/regulator.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
62 #include <dev/usb/usb.h>
63 #include <dev/usb/usbdi.h>
64 #include <dev/usb/usb_busdma.h>
65 #include <dev/usb/usb_process.h>
66 #include <dev/usb/usb_controller.h>
67 #include <dev/usb/usb_bus.h>
68 #include <dev/usb/controller/xhci.h>
69 #include <dev/usb/controller/xhcireg.h>
70
71 #include <arm/nvidia/tegra_pmc.h>
72
73 #include "usbdevs.h"
74
75 /* FPCI address space */
76 #define T_XUSB_CFG_0 0x000
77 #define T_XUSB_CFG_1 0x004
78 #define CFG_1_BUS_MASTER (1 << 2)
79 #define CFG_1_MEMORY_SPACE (1 << 1)
80 #define CFG_1_IO_SPACE (1 << 0)
81
82 #define T_XUSB_CFG_2 0x008
83 #define T_XUSB_CFG_3 0x00C
84 #define T_XUSB_CFG_4 0x010
85 #define CFG_4_BASE_ADDRESS(x) (((x) & 0x1FFFF) << 15)
86
87 #define T_XUSB_CFG_5 0x014
88 #define T_XUSB_CFG_ARU_MAILBOX_CMD 0x0E4
89 #define ARU_MAILBOX_CMD_INT_EN (1U << 31)
90 #define ARU_MAILBOX_CMD_DEST_XHCI (1 << 30)
91 #define ARU_MAILBOX_CMD_DEST_SMI (1 << 29)
92 #define ARU_MAILBOX_CMD_DEST_PME (1 << 28)
93 #define ARU_MAILBOX_CMD_DEST_FALC (1 << 27)
94
95 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN 0x0E8
96 #define ARU_MAILBOX_DATA_IN_DATA(x) (((x) & 0xFFFFFF) << 0)
97 #define ARU_MAILBOX_DATA_IN_TYPE(x) (((x) & 0x0000FF) << 24)
98
99 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT 0x0EC
100 #define ARU_MAILBOX_DATA_OUT_DATA(x) (((x) >> 0) & 0xFFFFFF)
101 #define ARU_MAILBOX_DATA_OUT_TYPE(x) (((x) >> 24) & 0x0000FF)
102
103 #define T_XUSB_CFG_ARU_MAILBOX_OWNER 0x0F0
104 #define ARU_MAILBOX_OWNER_SW 2
105 #define ARU_MAILBOX_OWNER_FW 1
106 #define ARU_MAILBOX_OWNER_NONE 0
107
108 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41C /* ! UNDOCUMENTED ! */
109 #define ARU_C11_CSBRANGE_PAGE(x) ((x) >> 9)
110 #define ARU_C11_CSBRANGE_ADDR(x) (0x800 + ((x) & 0x1FF))
111 #define XUSB_CFG_ARU_SMI_INTR 0x428 /* ! UNDOCUMENTED ! */
112 #define ARU_SMI_INTR_EN (1 << 3)
113 #define ARU_SMI_INTR_FW_HANG (1 << 1)
114 #define XUSB_CFG_ARU_RST 0x42C /* ! UNDOCUMENTED ! */
115 #define ARU_RST_RESET (1 << 0)
116
117 #define XUSB_HOST_CONFIGURATION 0x180
118 #define CONFIGURATION_CLKEN_OVERRIDE (1U<< 31)
119 #define CONFIGURATION_PW_NO_DEVSEL_ERR_CYA (1 << 19)
120 #define CONFIGURATION_INITIATOR_READ_IDLE (1 << 18)
121 #define CONFIGURATION_INITIATOR_WRITE_IDLE (1 << 17)
122 #define CONFIGURATION_WDATA_LEAD_CYA (1 << 15)
123 #define CONFIGURATION_WR_INTRLV_CYA (1 << 14)
124 #define CONFIGURATION_TARGET_READ_IDLE (1 << 11)
125 #define CONFIGURATION_TARGET_WRITE_IDLE (1 << 10)
126 #define CONFIGURATION_MSI_VEC_EMPTY (1 << 9)
127 #define CONFIGURATION_UFPCI_MSIAW (1 << 7)
128 #define CONFIGURATION_UFPCI_PWPASSPW (1 << 6)
129 #define CONFIGURATION_UFPCI_PASSPW (1 << 5)
130 #define CONFIGURATION_UFPCI_PWPASSNPW (1 << 4)
131 #define CONFIGURATION_DFPCI_PWPASSNPW (1 << 3)
132 #define CONFIGURATION_DFPCI_RSPPASSPW (1 << 2)
133 #define CONFIGURATION_DFPCI_PASSPW (1 << 1)
134 #define CONFIGURATION_EN_FPCI (1 << 0)
135
136 /* IPFS address space */
137 #define XUSB_HOST_FPCI_ERROR_MASKS 0x184
138 #define FPCI_ERROR_MASTER_ABORT (1 << 2)
139 #define FPCI_ERRORI_DATA_ERROR (1 << 1)
140 #define FPCI_ERROR_TARGET_ABORT (1 << 0)
141
142 #define XUSB_HOST_INTR_MASK 0x188
143 #define INTR_IP_INT_MASK (1 << 16)
144 #define INTR_MSI_MASK (1 << 8)
145 #define INTR_INT_MASK (1 << 0)
146
147 #define XUSB_HOST_CLKGATE_HYSTERESIS 0x1BC
148
149 /* CSB Falcon CPU */
150 #define XUSB_FALCON_CPUCTL 0x100
151 #define CPUCTL_STOPPED (1 << 5)
152 #define CPUCTL_HALTED (1 << 4)
153 #define CPUCTL_HRESET (1 << 3)
154 #define CPUCTL_SRESET (1 << 2)
155 #define CPUCTL_STARTCPU (1 << 1)
156 #define CPUCTL_IINVAL (1 << 0)
157
158 #define XUSB_FALCON_BOOTVEC 0x104
159 #define XUSB_FALCON_DMACTL 0x10C
160 #define XUSB_FALCON_IMFILLRNG1 0x154
161 #define IMFILLRNG1_TAG_HI(x) (((x) & 0xFFF) << 16)
162 #define IMFILLRNG1_TAG_LO(x) (((x) & 0xFFF) << 0)
163 #define XUSB_FALCON_IMFILLCTL 0x158
164
165 /* CSB mempool */
166 #define XUSB_CSB_MEMPOOL_APMAP 0x10181C
167 #define APMAP_BOOTPATH (1U << 31)
168
169 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR 0x101A00
170 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO 0x101A04
171 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI 0x101A08
172 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE 0x101A10
173 #define L2IMEMOP_SIZE_OFFSET(x) (((x) & 0x3FF) << 8)
174 #define L2IMEMOP_SIZE_SIZE(x) (((x) & 0x0FF) << 24)
175
176 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG 0x101A14
177 #define L2IMEMOP_INVALIDATE_ALL (0x40 << 24)
178 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << 24)
179
180 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101A18
181 #define L2IMEMOP_RESULT_VLD (1U << 31)
182
183 #define XUSB_CSB_IMEM_BLOCK_SIZE 256
184
185 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
186 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
187
188 /* MBOX commands. */
189 #define MBOX_CMD_MSG_ENABLED 1
190 #define MBOX_CMD_INC_FALC_CLOCK 2
191 #define MBOX_CMD_DEC_FALC_CLOCK 3
192 #define MBOX_CMD_INC_SSPI_CLOCK 4
193 #define MBOX_CMD_DEC_SSPI_CLOCK 5
194 #define MBOX_CMD_SET_BW 6
195 #define MBOX_CMD_SET_SS_PWR_GATING 7
196 #define MBOX_CMD_SET_SS_PWR_UNGATING 8
197 #define MBOX_CMD_SAVE_DFE_CTLE_CTX 9
198 #define MBOX_CMD_AIRPLANE_MODE_ENABLED 10
199 #define MBOX_CMD_AIRPLANE_MODE_DISABLED 11
200 #define MBOX_CMD_START_HSIC_IDLE 12
201 #define MBOX_CMD_STOP_HSIC_IDLE 13
202 #define MBOX_CMD_DBC_WAKE_STACK 14
203 #define MBOX_CMD_HSIC_PRETEND_CONNECT 15
204 #define MBOX_CMD_RESET_SSPI 16
205 #define MBOX_CMD_DISABLE_SS_LFPS_DETECTION 17
206 #define MBOX_CMD_ENABLE_SS_LFPS_DETECTION 18
207
208 /* MBOX responses. */
209 #define MBOX_CMD_ACK (0x80 + 0)
210 #define MBOX_CMD_NAK (0x80 + 1)
211
212
213 #define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v))
214 #define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r))
215 #define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v))
216 #define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r))
217
218 #define LOCK(_sc) mtx_lock(&(_sc)->mtx)
219 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
220 #define SLEEP(_sc, timeout) \
221 mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout);
222 #define LOCK_INIT(_sc) \
223 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_xhci", MTX_DEF)
224 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
225 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
226 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
227
228 struct tegra_xusb_fw_hdr {
229 uint32_t boot_loadaddr_in_imem;
230 uint32_t boot_codedfi_offset;
231 uint32_t boot_codetag;
232 uint32_t boot_codesize;
233
234 uint32_t phys_memaddr;
235 uint16_t reqphys_memsize;
236 uint16_t alloc_phys_memsize;
237
238 uint32_t rodata_img_offset;
239 uint32_t rodata_section_start;
240 uint32_t rodata_section_end;
241 uint32_t main_fnaddr;
242
243 uint32_t fwimg_cksum;
244 uint32_t fwimg_created_time;
245
246 uint32_t imem_resident_start;
247 uint32_t imem_resident_end;
248 uint32_t idirect_start;
249 uint32_t idirect_end;
250 uint32_t l2_imem_start;
251 uint32_t l2_imem_end;
252 uint32_t version_id;
253 uint8_t init_ddirect;
254 uint8_t reserved[3];
255 uint32_t phys_addr_log_buffer;
256 uint32_t total_log_entries;
257 uint32_t dequeue_ptr;
258 uint32_t dummy[2];
259 uint32_t fwimg_len;
260 uint8_t magic[8];
261 uint32_t ss_low_power_entry_timeout;
262 uint8_t num_hsic_port;
263 uint8_t ss_portmap;
264 uint8_t build;
265 uint8_t padding[137]; /* Pad to 256 bytes */
266 };
267
268 /* Compatible devices. */
269 static struct ofw_compat_data compat_data[] = {
270 {"nvidia,tegra124-xusb", 1},
271 {NULL, 0}
272 };
273
274 struct tegra_xhci_softc {
275 struct xhci_softc xhci_softc;
276 device_t dev;
277 struct mtx mtx;
278 struct resource *mem_res_fpci;
279 struct resource *mem_res_ipfs;
280 struct resource *irq_res_mbox;
281 void *irq_hdl_mbox;
282
283 clk_t clk_xusb_host;
284 clk_t clk_xusb_gate;
285 clk_t clk_xusb_falcon_src;
286 clk_t clk_xusb_ss;
287 clk_t clk_xusb_hs_src;
288 clk_t clk_xusb_fs_src;
289 hwreset_t hwreset_xusb_host;
290 hwreset_t hwreset_xusb_ss;
291 regulator_t supply_avddio_pex;
292 regulator_t supply_dvddio_pex;
293 regulator_t supply_avdd_usb;
294 regulator_t supply_avdd_pll_utmip;
295 regulator_t supply_avdd_pll_erefe;
296 regulator_t supply_avdd_usb_ss_pll;
297 regulator_t supply_hvdd_usb_ss;
298 regulator_t supply_hvdd_usb_ss_pll_e;
299 phy_t phy_usb2_0;
300 phy_t phy_usb2_1;
301 phy_t phy_usb2_2;
302 phy_t phy_usb3_0;
303
304 struct intr_config_hook irq_hook;
305 bool xhci_inited;
306 char *fw_name;
307 vm_offset_t fw_vaddr;
308 vm_size_t fw_size;
309 };
310
311 static uint32_t
CSB_RD4(struct tegra_xhci_softc * sc,uint32_t addr)312 CSB_RD4(struct tegra_xhci_softc *sc, uint32_t addr)
313 {
314
315 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr));
316 return (FPCI_RD4(sc, ARU_C11_CSBRANGE_ADDR(addr)));
317 }
318
319 static void
CSB_WR4(struct tegra_xhci_softc * sc,uint32_t addr,uint32_t val)320 CSB_WR4(struct tegra_xhci_softc *sc, uint32_t addr, uint32_t val)
321 {
322
323 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr));
324 FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val);
325 }
326
327 static int
get_fdt_resources(struct tegra_xhci_softc * sc,phandle_t node)328 get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node)
329 {
330 int rv;
331
332 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply",
333 &sc->supply_avddio_pex);
334 if (rv != 0) {
335 device_printf(sc->dev,
336 "Cannot get 'avddio-pex' regulator\n");
337 return (ENXIO);
338 }
339 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply",
340 &sc->supply_dvddio_pex);
341 if (rv != 0) {
342 device_printf(sc->dev,
343 "Cannot get 'dvddio-pex' regulator\n");
344 return (ENXIO);
345 }
346 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-supply",
347 &sc->supply_avdd_usb);
348 if (rv != 0) {
349 device_printf(sc->dev,
350 "Cannot get 'avdd-usb' regulator\n");
351 return (ENXIO);
352 }
353 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-utmip-supply",
354 &sc->supply_avdd_pll_utmip);
355 if (rv != 0) {
356 device_printf(sc->dev,
357 "Cannot get 'avdd-pll-utmip' regulator\n");
358 return (ENXIO);
359 }
360 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply",
361 &sc->supply_avdd_pll_erefe);
362 if (rv != 0) {
363 device_printf(sc->dev,
364 "Cannot get 'avdd-pll-erefe' regulator\n");
365 return (ENXIO);
366 }
367 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-ss-pll-supply",
368 &sc->supply_avdd_usb_ss_pll);
369 if (rv != 0) {
370 device_printf(sc->dev,
371 "Cannot get 'avdd-usb-ss-pll' regulator\n");
372 return (ENXIO);
373 }
374 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-usb-ss-supply",
375 &sc->supply_hvdd_usb_ss);
376 if (rv != 0) {
377 device_printf(sc->dev,
378 "Cannot get 'hvdd-usb-ss' regulator\n");
379 return (ENXIO);
380 }
381 rv = regulator_get_by_ofw_property(sc->dev, 0,
382 "hvdd-usb-ss-pll-e-supply", &sc->supply_hvdd_usb_ss_pll_e);
383 if (rv != 0) {
384 device_printf(sc->dev,
385 "Cannot get 'hvdd-usb-ss-pll-e' regulator\n");
386 return (ENXIO);
387 }
388
389 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host",
390 &sc->hwreset_xusb_host);
391 if (rv != 0) {
392 device_printf(sc->dev, "Cannot get 'xusb_host' reset\n");
393 return (ENXIO);
394 }
395 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss",
396 &sc->hwreset_xusb_ss);
397 if (rv != 0) {
398 device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n");
399 return (ENXIO);
400 }
401
402 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-0", &sc->phy_usb2_0);
403 if (rv != 0) {
404 device_printf(sc->dev, "Cannot get 'usb2-0' phy\n");
405 return (ENXIO);
406 }
407 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-1", &sc->phy_usb2_1);
408 if (rv != 0) {
409 device_printf(sc->dev, "Cannot get 'usb2-1' phy\n");
410 return (ENXIO);
411 }
412 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-2", &sc->phy_usb2_2);
413 if (rv != 0) {
414 device_printf(sc->dev, "Cannot get 'usb2-2' phy\n");
415 return (ENXIO);
416 }
417 rv = phy_get_by_ofw_name(sc->dev, 0, "usb3-0", &sc->phy_usb3_0);
418 if (rv != 0) {
419 device_printf(sc->dev, "Cannot get 'usb3-0' phy\n");
420 return (ENXIO);
421 }
422
423 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host",
424 &sc->clk_xusb_host);
425 if (rv != 0) {
426 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n");
427 return (ENXIO);
428 }
429 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src",
430 &sc->clk_xusb_falcon_src);
431 if (rv != 0) {
432 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n");
433 return (ENXIO);
434 }
435 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss",
436 &sc->clk_xusb_ss);
437 if (rv != 0) {
438 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n");
439 return (ENXIO);
440 }
441 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src",
442 &sc->clk_xusb_hs_src);
443 if (rv != 0) {
444 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n");
445 return (ENXIO);
446 }
447 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src",
448 &sc->clk_xusb_fs_src);
449 if (rv != 0) {
450 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n");
451 return (ENXIO);
452 }
453 rv = clk_get_by_ofw_index_prop(sc->dev, 0, "freebsd,clock-xusb-gate", 0,
454 &sc->clk_xusb_gate);
455 if (rv != 0) {
456 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n");
457 return (ENXIO);
458 }
459 return (0);
460 }
461
462 static int
enable_fdt_resources(struct tegra_xhci_softc * sc)463 enable_fdt_resources(struct tegra_xhci_softc *sc)
464 {
465 int rv;
466
467 rv = hwreset_assert(sc->hwreset_xusb_host);
468 if (rv != 0) {
469 device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n");
470 return (rv);
471 }
472 rv = hwreset_assert(sc->hwreset_xusb_ss);
473 if (rv != 0) {
474 device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n");
475 return (rv);
476 }
477
478 rv = regulator_enable(sc->supply_avddio_pex);
479 if (rv != 0) {
480 device_printf(sc->dev,
481 "Cannot enable 'avddio_pex' regulator\n");
482 return (rv);
483 }
484 rv = regulator_enable(sc->supply_dvddio_pex);
485 if (rv != 0) {
486 device_printf(sc->dev,
487 "Cannot enable 'dvddio_pex' regulator\n");
488 return (rv);
489 }
490 rv = regulator_enable(sc->supply_avdd_usb);
491 if (rv != 0) {
492 device_printf(sc->dev,
493 "Cannot enable 'avdd_usb' regulator\n");
494 return (rv);
495 }
496 rv = regulator_enable(sc->supply_avdd_pll_utmip);
497 if (rv != 0) {
498 device_printf(sc->dev,
499 "Cannot enable 'avdd_pll_utmip-5v' regulator\n");
500 return (rv);
501 }
502 rv = regulator_enable(sc->supply_avdd_pll_erefe);
503 if (rv != 0) {
504 device_printf(sc->dev,
505 "Cannot enable 'avdd_pll_erefe' regulator\n");
506 return (rv);
507 }
508 rv = regulator_enable(sc->supply_avdd_usb_ss_pll);
509 if (rv != 0) {
510 device_printf(sc->dev,
511 "Cannot enable 'avdd_usb_ss_pll' regulator\n");
512 return (rv);
513 }
514 rv = regulator_enable(sc->supply_hvdd_usb_ss);
515 if (rv != 0) {
516 device_printf(sc->dev,
517 "Cannot enable 'hvdd_usb_ss' regulator\n");
518 return (rv);
519 }
520 rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e);
521 if (rv != 0) {
522 device_printf(sc->dev,
523 "Cannot enable 'hvdd_usb_ss_pll_e' regulator\n");
524 return (rv);
525 }
526
527 /* Power off XUSB host and XUSB SS domains. */
528 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
529 if (rv != 0) {
530 device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n");
531 return (rv);
532 }
533 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
534 if (rv != 0) {
535 device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n");
536 return (rv);
537 }
538
539 /* Setup XUSB ss_src clock first */
540 clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);
541 if (rv != 0)
542 return (rv);
543
544 /* The XUSB gate clock must be enabled before XUSBA can be powered. */
545 rv = clk_enable(sc->clk_xusb_gate);
546 if (rv != 0) {
547 device_printf(sc->dev,
548 "Cannot enable 'xusb_gate' clock\n");
549 return (rv);
550 }
551
552 /* Power on XUSB host and XUSB SS domains. */
553 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
554 sc->clk_xusb_host, sc->hwreset_xusb_host);
555 if (rv != 0) {
556 device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n");
557 return (rv);
558 }
559 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
560 sc->clk_xusb_ss, sc->hwreset_xusb_ss);
561 if (rv != 0) {
562 device_printf(sc->dev, "Cannot powerup 'xusba' domain\n");
563 return (rv);
564 }
565
566 /* Enable rest of clocks */
567 rv = clk_enable(sc->clk_xusb_falcon_src);
568 if (rv != 0) {
569 device_printf(sc->dev,
570 "Cannot enable 'xusb_falcon_src' clock\n");
571 return (rv);
572 }
573 rv = clk_enable(sc->clk_xusb_fs_src);
574 if (rv != 0) {
575 device_printf(sc->dev,
576 "Cannot enable 'xusb_fs_src' clock\n");
577 return (rv);
578 }
579 rv = clk_enable(sc->clk_xusb_hs_src);
580 if (rv != 0) {
581 device_printf(sc->dev,
582 "Cannot enable 'xusb_hs_src' clock\n");
583 return (rv);
584 }
585
586 rv = phy_enable(sc->phy_usb2_0);
587 if (rv != 0) {
588 device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
589 return (rv);
590 }
591 rv = phy_enable(sc->phy_usb2_1);
592 if (rv != 0) {
593 device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
594 return (rv);
595 }
596 rv = phy_enable(sc->phy_usb2_2);
597 if (rv != 0) {
598 device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
599 return (rv);
600 }
601 rv = phy_enable(sc->phy_usb3_0);
602 if (rv != 0) {
603 device_printf(sc->dev, "Cannot enable USB3_0 phy\n");
604 return (rv);
605 }
606
607 return (0);
608 }
609
610 /* Respond by ACK/NAK back to FW */
611 static void
mbox_send_ack(struct tegra_xhci_softc * sc,uint32_t cmd,uint32_t data)612 mbox_send_ack(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data)
613 {
614 uint32_t reg;
615
616 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data);
617 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);
618
619 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);
620 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN;
621 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);
622 }
623
624 /* Sent command to FW */
625 static int
mbox_send_cmd(struct tegra_xhci_softc * sc,uint32_t cmd,uint32_t data)626 mbox_send_cmd(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data)
627 {
628 uint32_t reg;
629 int i;
630
631 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);
632 if (reg != ARU_MAILBOX_OWNER_NONE) {
633 device_printf(sc->dev,
634 "CPU mailbox is busy: 0x%08X\n", reg);
635 return (EBUSY);
636 }
637 /* XXX Is this right? Retry loop? Wait before send? */
638 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW);
639 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);
640 if (reg != ARU_MAILBOX_OWNER_SW) {
641 device_printf(sc->dev,
642 "Cannot acquire CPU mailbox: 0x%08X\n", reg);
643 return (EBUSY);
644 }
645 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data);
646 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);
647
648 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);
649 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN;
650 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);
651
652 for (i = 250; i > 0; i--) {
653 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);
654 if (reg == ARU_MAILBOX_OWNER_NONE)
655 break;
656 DELAY(100);
657 }
658 if (i <= 0) {
659 device_printf(sc->dev,
660 "Command response timeout: 0x%08X\n", reg);
661 return (ETIMEDOUT);
662 }
663
664 return(0);
665 }
666
667 static void
process_msg(struct tegra_xhci_softc * sc,uint32_t req_cmd,uint32_t req_data,uint32_t * resp_cmd,uint32_t * resp_data)668 process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data,
669 uint32_t *resp_cmd, uint32_t *resp_data)
670 {
671 uint64_t freq;
672 int rv;
673
674 /* In most cases, data are echoed back. */
675 *resp_data = req_data;
676 switch (req_cmd) {
677 case MBOX_CMD_INC_FALC_CLOCK:
678 case MBOX_CMD_DEC_FALC_CLOCK:
679 rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL,
680 0);
681 if (rv == 0) {
682 rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq);
683 *resp_data = (uint32_t)(freq / 1000);
684 }
685 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;
686 break;
687
688 case MBOX_CMD_INC_SSPI_CLOCK:
689 case MBOX_CMD_DEC_SSPI_CLOCK:
690 rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL,
691 0);
692 if (rv == 0) {
693 rv = clk_get_freq(sc->clk_xusb_ss, &freq);
694 *resp_data = (uint32_t)(freq / 1000);
695 }
696 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;
697 break;
698
699 case MBOX_CMD_SET_BW:
700 /* No respense is expected. */
701 *resp_cmd = 0;
702 break;
703
704 case MBOX_CMD_SET_SS_PWR_GATING:
705 case MBOX_CMD_SET_SS_PWR_UNGATING:
706 *resp_cmd = MBOX_CMD_NAK;
707 break;
708
709 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
710 /* Not implemented yet. */
711 *resp_cmd = MBOX_CMD_ACK;
712 break;
713
714
715 case MBOX_CMD_START_HSIC_IDLE:
716 case MBOX_CMD_STOP_HSIC_IDLE:
717 /* Not implemented yet. */
718 *resp_cmd = MBOX_CMD_NAK;
719 break;
720
721 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
722 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
723 /* Not implemented yet. */
724 *resp_cmd = MBOX_CMD_NAK;
725 break;
726
727 case MBOX_CMD_AIRPLANE_MODE_ENABLED:
728 case MBOX_CMD_AIRPLANE_MODE_DISABLED:
729 case MBOX_CMD_DBC_WAKE_STACK:
730 case MBOX_CMD_HSIC_PRETEND_CONNECT:
731 case MBOX_CMD_RESET_SSPI:
732 device_printf(sc->dev,
733 "Received unused/unexpected command: %u\n", req_cmd);
734 *resp_cmd = 0;
735 break;
736
737 default:
738 device_printf(sc->dev,
739 "Received unknown command: %u\n", req_cmd);
740 }
741 }
742
743 static void
intr_mbox(void * arg)744 intr_mbox(void *arg)
745 {
746 struct tegra_xhci_softc *sc;
747 uint32_t reg, msg, resp_cmd, resp_data;
748
749 sc = (struct tegra_xhci_softc *)arg;
750
751 /* Clear interrupt first */
752 reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR);
753 FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg);
754 if (reg & ARU_SMI_INTR_FW_HANG) {
755 device_printf(sc->dev,
756 "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n",
757 CSB_RD4(sc, XUSB_FALCON_CPUCTL));
758 }
759
760 msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT);
761 resp_cmd = 0;
762 process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg),
763 ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data);
764 if (resp_cmd != 0)
765 mbox_send_ack(sc, resp_cmd, resp_data);
766 else
767 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER,
768 ARU_MAILBOX_OWNER_NONE);
769
770 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);
771 reg &= ~ARU_MAILBOX_CMD_DEST_SMI;
772 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);
773
774 }
775
776 static int
load_fw(struct tegra_xhci_softc * sc)777 load_fw(struct tegra_xhci_softc *sc)
778 {
779 const struct firmware *fw;
780 const struct tegra_xusb_fw_hdr *fw_hdr;
781 vm_paddr_t fw_paddr, fw_base;
782 vm_offset_t fw_vaddr;
783 vm_size_t fw_size;
784 uint32_t code_tags, code_size;
785 struct clocktime fw_clock;
786 struct timespec fw_timespec;
787 int i;
788
789 /* Reset ARU */
790 FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET);
791 DELAY(3000);
792
793 /* Check if FALCON already runs */
794 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) {
795 device_printf(sc->dev,
796 "XUSB CPU is already loaded, CPUCTL: 0x%08X\n",
797 CSB_RD4(sc, XUSB_FALCON_CPUCTL));
798 return (0);
799 }
800
801 fw = firmware_get(sc->fw_name);
802 if (fw == NULL) {
803 device_printf(sc->dev, "Cannot read xusb firmware\n");
804 return (ENOENT);
805 }
806
807 /* Allocate uncached memory and copy firmware into. */
808 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data;
809 fw_size = fw_hdr->fwimg_len;
810
811 fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0,
812 VM_MEMATTR_UNCACHEABLE);
813 fw_paddr = vtophys(fw_vaddr);
814 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr;
815 memcpy((void *)fw_vaddr, fw->data, fw_size);
816
817 firmware_put(fw, FIRMWARE_UNLOAD);
818 sc->fw_vaddr = fw_vaddr;
819 sc->fw_size = fw_size;
820
821 /* Setup firmware physical address and size. */
822 fw_base = fw_paddr + sizeof(*fw_hdr);
823 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size);
824 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF);
825 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32);
826 CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH);
827
828 /* Invalidate full L2IMEM context. */
829 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG,
830 L2IMEMOP_INVALIDATE_ALL);
831
832 /* Program load of L2IMEM by boot code. */
833 code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE);
834 code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE);
835 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE,
836 L2IMEMOP_SIZE_OFFSET(code_tags) |
837 L2IMEMOP_SIZE_SIZE(code_size));
838
839 /* Execute L2IMEM boot code fetch. */
840 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG,
841 L2IMEMOP_LOAD_LOCKED_RESULT);
842
843 /* Program FALCON auto-fill range and block count */
844 CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size);
845 CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1,
846 IMFILLRNG1_TAG_LO(code_tags) |
847 IMFILLRNG1_TAG_HI(code_tags + code_size));
848
849 CSB_WR4(sc, XUSB_FALCON_DMACTL, 0);
850 /* Wait for CPU */
851 for (i = 500; i > 0; i--) {
852 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) &
853 L2IMEMOP_RESULT_VLD)
854 break;
855 DELAY(100);
856 }
857 if (i <= 0) {
858 device_printf(sc->dev, "Timedout while wating for DMA, "
859 "state: 0x%08X\n",
860 CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT));
861 return (ETIMEDOUT);
862 }
863
864 /* Boot FALCON cpu */
865 CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag);
866 CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU);
867
868 /* Wait for CPU */
869 for (i = 50; i > 0; i--) {
870 if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED)
871 break;
872 DELAY(100);
873 }
874 if (i <= 0) {
875 device_printf(sc->dev, "Timedout while wating for FALCON cpu, "
876 "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL));
877 return (ETIMEDOUT);
878 }
879
880 fw_timespec.tv_sec = fw_hdr->fwimg_created_time;
881 fw_timespec.tv_nsec = 0;
882 clock_ts_to_ct(&fw_timespec, &fw_clock);
883 device_printf(sc->dev,
884 " Falcon firmware version: %02X.%02X.%04X,"
885 " (%d/%d/%d %d:%02d:%02d UTC)\n",
886 (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF,
887 fw_hdr->version_id & 0xFFFF,
888 fw_clock.day, fw_clock.mon, fw_clock.year,
889 fw_clock.hour, fw_clock.min, fw_clock.sec);
890
891 return (0);
892 }
893
894 static int
init_hw(struct tegra_xhci_softc * sc)895 init_hw(struct tegra_xhci_softc *sc)
896 {
897 int rv;
898 uint32_t reg;
899 rman_res_t base_addr;
900
901 base_addr = rman_get_start(sc->xhci_softc.sc_io_res);
902
903 /* Enable FPCI access */
904 reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION);
905 reg |= CONFIGURATION_EN_FPCI;
906 IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg);
907 IPFS_RD4(sc, XUSB_HOST_CONFIGURATION);
908
909
910 /* Program bar for XHCI base address */
911 reg = FPCI_RD4(sc, T_XUSB_CFG_4);
912 reg &= ~CFG_4_BASE_ADDRESS(~0);
913 reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15);
914 FPCI_WR4(sc, T_XUSB_CFG_4, reg);
915 FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32));
916
917 /* Enable bus master */
918 reg = FPCI_RD4(sc, T_XUSB_CFG_1);
919 reg |= CFG_1_IO_SPACE;
920 reg |= CFG_1_MEMORY_SPACE;
921 reg |= CFG_1_BUS_MASTER;
922 FPCI_WR4(sc, T_XUSB_CFG_1, reg);
923
924 /* Enable Interrupts */
925 reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK);
926 reg |= INTR_IP_INT_MASK;
927 IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg);
928
929 /* Set hysteresis */
930 IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128);
931
932 rv = load_fw(sc);
933 if (rv != 0)
934 return rv;
935 return (0);
936 }
937
938 static int
tegra_xhci_probe(device_t dev)939 tegra_xhci_probe(device_t dev)
940 {
941
942 if (!ofw_bus_status_okay(dev))
943 return (ENXIO);
944
945 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
946 device_set_desc(dev, "Nvidia Tegra XHCI controller");
947 return (BUS_PROBE_DEFAULT);
948 }
949 return (ENXIO);
950 }
951
952 static int
tegra_xhci_detach(device_t dev)953 tegra_xhci_detach(device_t dev)
954 {
955 struct tegra_xhci_softc *sc;
956 struct xhci_softc *xsc;
957
958 sc = device_get_softc(dev);
959 xsc = &sc->xhci_softc;
960
961 /* during module unload there are lots of children leftover */
962 device_delete_children(dev);
963 if (sc->xhci_inited) {
964 usb_callout_drain(&xsc->sc_callout);
965 xhci_halt_controller(xsc);
966 }
967
968 if (xsc->sc_irq_res && xsc->sc_intr_hdl) {
969 bus_teardown_intr(dev, xsc->sc_irq_res, xsc->sc_intr_hdl);
970 xsc->sc_intr_hdl = NULL;
971 }
972 if (xsc->sc_irq_res) {
973 bus_release_resource(dev, SYS_RES_IRQ,
974 rman_get_rid(xsc->sc_irq_res), xsc->sc_irq_res);
975 xsc->sc_irq_res = NULL;
976 }
977 if (xsc->sc_io_res != NULL) {
978 bus_release_resource(dev, SYS_RES_MEMORY,
979 rman_get_rid(xsc->sc_io_res), xsc->sc_io_res);
980 xsc->sc_io_res = NULL;
981 }
982 if (sc->xhci_inited)
983 xhci_uninit(xsc);
984 if (sc->irq_hdl_mbox != NULL)
985 bus_teardown_intr(dev, sc->irq_res_mbox, sc->irq_hdl_mbox);
986 if (sc->fw_vaddr != 0)
987 kmem_free(sc->fw_vaddr, sc->fw_size);
988 LOCK_DESTROY(sc);
989 return (0);
990 }
991
992 static int
tegra_xhci_attach(device_t dev)993 tegra_xhci_attach(device_t dev)
994 {
995 struct tegra_xhci_softc *sc;
996 struct xhci_softc *xsc;
997 int rv, rid;
998 phandle_t node;
999
1000 sc = device_get_softc(dev);
1001 sc->dev = dev;
1002 sc->fw_name = "tegra124_xusb_fw";
1003 node = ofw_bus_get_node(dev);
1004 xsc = &sc->xhci_softc;
1005 LOCK_INIT(sc);
1006
1007 rv = get_fdt_resources(sc, node);
1008 if (rv != 0) {
1009 rv = ENXIO;
1010 goto error;
1011 }
1012 rv = enable_fdt_resources(sc);
1013 if (rv != 0) {
1014 rv = ENXIO;
1015 goto error;
1016 }
1017
1018 /* Allocate resources. */
1019 rid = 0;
1020 xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1021 RF_ACTIVE);
1022 if (xsc->sc_io_res == NULL) {
1023 device_printf(dev,
1024 "Could not allocate HCD memory resources\n");
1025 rv = ENXIO;
1026 goto error;
1027 }
1028 rid = 1;
1029 sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1030 RF_ACTIVE);
1031 if (sc->mem_res_fpci == NULL) {
1032 device_printf(dev,
1033 "Could not allocate FPCI memory resources\n");
1034 rv = ENXIO;
1035 goto error;
1036 }
1037 rid = 2;
1038 sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1039 RF_ACTIVE);
1040 if (sc->mem_res_ipfs == NULL) {
1041 device_printf(dev,
1042 "Could not allocate IPFS memory resources\n");
1043 rv = ENXIO;
1044 goto error;
1045 }
1046
1047 rid = 0;
1048 xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1049 RF_ACTIVE);
1050 if (xsc->sc_irq_res == NULL) {
1051 device_printf(dev, "Could not allocate HCD IRQ resources\n");
1052 rv = ENXIO;
1053 goto error;
1054 }
1055 rid = 1;
1056 sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1057 RF_ACTIVE);
1058 if (sc->irq_res_mbox == NULL) {
1059 device_printf(dev, "Could not allocate MBOX IRQ resources\n");
1060 rv = ENXIO;
1061 goto error;
1062 }
1063
1064 rv = init_hw(sc);
1065 if (rv != 0) {
1066 device_printf(dev, "Could not initialize XUSB hardware\n");
1067 goto error;
1068 }
1069
1070 /* Wakeup and enable firmaware */
1071 rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0);
1072 if (rv != 0) {
1073 device_printf(sc->dev, "Could not enable XUSB firmware\n");
1074 goto error;
1075 }
1076
1077 /* Fill data for XHCI driver. */
1078 xsc->sc_bus.parent = dev;
1079 xsc->sc_bus.devices = xsc->sc_devices;
1080 xsc->sc_bus.devices_max = XHCI_MAX_DEVICES;
1081
1082 xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res);
1083 xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res);
1084 xsc->sc_io_size = rman_get_size(xsc->sc_io_res);
1085 strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor));
1086
1087 /* Add USB bus device. */
1088 xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1);
1089 if (xsc->sc_bus.bdev == NULL) {
1090 device_printf(sc->dev, "Could not add USB device\n");
1091 rv = ENXIO;
1092 goto error;
1093 }
1094 device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus);
1095 device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller");
1096
1097 rv = xhci_init(xsc, sc->dev, 1);
1098 if (rv != 0) {
1099 device_printf(sc->dev, "USB init failed: %d\n", rv);
1100 goto error;
1101 }
1102 sc->xhci_inited = true;
1103 rv = xhci_start_controller(xsc);
1104 if (rv != 0) {
1105 device_printf(sc->dev,
1106 "Could not start XHCI controller: %d\n", rv);
1107 goto error;
1108 }
1109
1110 rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE,
1111 NULL, intr_mbox, sc, &sc->irq_hdl_mbox);
1112 if (rv != 0) {
1113 device_printf(dev, "Could not setup error IRQ: %d\n",rv);
1114 xsc->sc_intr_hdl = NULL;
1115 goto error;
1116 }
1117
1118 rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1119 NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl);
1120 if (rv != 0) {
1121 device_printf(dev, "Could not setup error IRQ: %d\n",rv);
1122 xsc->sc_intr_hdl = NULL;
1123 goto error;
1124 }
1125
1126 /* Probe the bus. */
1127 rv = device_probe_and_attach(xsc->sc_bus.bdev);
1128 if (rv != 0) {
1129 device_printf(sc->dev, "Could not initialize USB: %d\n", rv);
1130 goto error;
1131 }
1132
1133 return (0);
1134
1135 error:
1136 panic("XXXXX");
1137 tegra_xhci_detach(dev);
1138 return (rv);
1139 }
1140
1141 static device_method_t xhci_methods[] = {
1142 /* Device interface */
1143 DEVMETHOD(device_probe, tegra_xhci_probe),
1144 DEVMETHOD(device_attach, tegra_xhci_attach),
1145 DEVMETHOD(device_detach, tegra_xhci_detach),
1146 DEVMETHOD(device_suspend, bus_generic_suspend),
1147 DEVMETHOD(device_resume, bus_generic_resume),
1148 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1149
1150 /* Bus interface */
1151 DEVMETHOD(bus_print_child, bus_generic_print_child),
1152
1153 DEVMETHOD_END
1154 };
1155
1156 static devclass_t xhci_devclass;
1157 static DEFINE_CLASS_0(xhci, xhci_driver, xhci_methods,
1158 sizeof(struct tegra_xhci_softc));
1159 DRIVER_MODULE(tegra_xhci, simplebus, xhci_driver, xhci_devclass, NULL, NULL);
1160 MODULE_DEPEND(tegra_xhci, usb, 1, 1, 1);
1161