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Searched refs:__SHIFTIN (Results 1 – 10 of 10) sorted by relevance

/freebsd-12-stable/sys/dev/qat/
Dqatreg.h73 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
214 (__SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \
216 __SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \
218 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE))
222 (__SHIFTIN((wm_nf), ETR_RING_CONFIG_NEAR_FULL_WM) | \
223 __SHIFTIN((wm_ne), ETR_RING_CONFIG_NEAR_EMPTY_WM) | \
224 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE))
1372 __SHIFTIN(mode, HW_AUTH_CONFIG_MODE) | \
1373 __SHIFTIN(algo, HW_AUTH_CONFIG_ALGO) | \
1374 __SHIFTIN(cmp_len, HW_AUTH_CONFIG_CMPLEN)
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Dqat_hw15reg.h539 #define LA_FLAGS_PROTO_SNOW_3G __SHIFTIN(4, LA_FLAGS_PROTO)
540 #define LA_FLAGS_PROTO_GCM __SHIFTIN(2, LA_FLAGS_PROTO)
541 #define LA_FLAGS_PROTO_CCM __SHIFTIN(1, LA_FLAGS_PROTO)
542 #define LA_FLAGS_PROTO_NO __SHIFTIN(0, LA_FLAGS_PROTO)
Dqatvar.h921 offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) | in qat_ae_local_write_4()
932 offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) | in qat_ae_local_read_4()
942 offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_XFER_AE_MASK) | in qat_ae_xfer_write_4()
943 __SHIFTIN(offset, AE_XFER_CSR_MASK); in qat_ae_xfer_write_4()
Dqat_ae.c723 ctxen |= __SHIFTIN(ctx_mask, CTX_ENABLES_ENABLE); in qat_ae_enable_ctx()
734 ctxen &= ~(__SHIFTIN(ctx_mask & AE_ALL_CTX, CTX_ENABLES_ENABLE)); in qat_ae_disable_ctx()
864 val |= __SHIFTIN(cs_reload, AE_MISC_CONTROL_CS_RELOAD) | in qat_ae_set_reload_ustore()
865 __SHIFTIN(shared_mode, AE_MISC_CONTROL_ONE_CTX_RELOAD); in qat_ae_set_reload_ustore()
1040 reset &= ~(__SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_RESET_AE_MASK)); in qat_ae_clear_reset()
1041 reset &= ~(__SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_RESET_ACCEL_MASK)); in qat_ae_clear_reset()
1050 } while ((__SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_RESET_AE_MASK) | in qat_ae_clear_reset()
1051 __SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_RESET_ACCEL_MASK)) in qat_ae_clear_reset()
1056 clock |= __SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_CLK_EN_AE_MASK); in qat_ae_clear_reset()
1057 clock |= __SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK); in qat_ae_clear_reset()
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Dqat.c868 dest[nae] = __SHIFTIN(ae, ETR_AP_DEST_AE) | in qat_etr_ap_bank_set_ring_dest()
869 __SHIFTIN(mailbox, ETR_AP_DEST_MAILBOX) | in qat_etr_ap_bank_set_ring_dest()
/freebsd-12-stable/sys/dev/bwi/
Dif_bwi.c337 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | in bwi_setup_desc32()
338 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); in bwi_setup_desc32()
340 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | in bwi_setup_desc32()
341 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); in bwi_setup_desc32()
810 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | in bwi_bbp_attach()
811 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); in bwi_bbp_attach()
964 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | in bwi_bus_init()
965 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); in bwi_bus_init()
2341 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | in bwi_init_tx_ring32()
2342 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, in bwi_init_tx_ring32()
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Dbitops.h80 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
Dbwimac.c310 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | in bwi_mac_init()
311 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); in bwi_mac_init()
466 state_lo &= ~__SHIFTIN(BWI_STATE_LO_FLAG_PHYRST, in bwi_mac_reset()
532 __SHIFTIN(tpctl->tp_ctrl1, BWI_RFR_TXPWR1_MASK)); in bwi_mac_set_tpctl_11bg()
Dbwiphy.c232 __SHIFTIN(bbp_atten, mask)); in bwi_phy_set_bbp_atten()
239 __SHIFTIN(bbp_atten, mask)); in bwi_phy_set_bbp_atten()
Dbwirf.c2213 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) | in bwi_rf_set_nrssi_thr_11g()
2214 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK); in bwi_rf_set_nrssi_thr_11g()
2231 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) | in bwi_rf_clear_tssi()
2232 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK); in bwi_rf_clear_tssi()