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Searched refs:ZERO_EXTEND_VECTOR_INREG (Results 1 – 15 of 15) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h780 ZERO_EXTEND_VECTOR_INREG, enumerator
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp69 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
423 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
963 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
2213 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorOperand()
3088 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
3571 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3696 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3714 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4674 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
DLegalizeVectorOps.cpp438 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
749 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
DSelectionDAGDumper.cpp341 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
DTargetLowering.cpp798 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyMultipleUseDemandedBits()
1871 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1876 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
1950 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
2790 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedVectorElts()
2808 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in SimplifyDemandedVectorElts()
DLegalizeIntegerTypes.cpp122 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
4926 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
DDAGCombiner.cpp1679 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitEXTEND_VECTOR_INREG(N); in visit()
10400 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
10452 Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG; in tryToFoldExtendOfConstant()
12045 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in visitSIGN_EXTEND_INREG()
12050 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
20868 Opcode != ISD::ZERO_EXTEND_VECTOR_INREG) in combineTruncationShuffle()
DSelectionDAG.cpp3251 case ISD::ZERO_EXTEND_VECTOR_INREG: { in computeKnownBits()
4981 case ISD::ZERO_EXTEND_VECTOR_INREG: in getNode()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp101 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
164 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
1646 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op), in LowerHvxExtend()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp838 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp382 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
5526 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
5817 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td430 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp1162 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1384 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1631 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
2043 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG); in X86TargetLowering()
6339 case ISD::ZERO_EXTEND_VECTOR_INREG: in getOpcode_EXTEND()
6355 case ISD::ZERO_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6356 return ISD::ZERO_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
7890 case ISD::ZERO_EXTEND_VECTOR_INREG: in getFauxShuffleMask()
10034 IndicesVec = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(IndicesVec), in createVariablePermute()
25010 ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt), in getTargetVShiftNode()
[all …]
DX86ISelDAGToDAG.cpp1055 : ISD::ZERO_EXTEND_VECTOR_INREG; in PreprocessISelDAG()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp17048 SubOpcd0 == ISD::ZERO_EXTEND_VECTOR_INREG) && in combineABS()
17050 SubOpcd1 == ISD::ZERO_EXTEND_VECTOR_INREG)) { in combineABS()