1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28 /*
29 XHCI options:
30 -s <n>,xhci,{devices}
31
32 devices:
33 tablet USB tablet mouse
34 */
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD: stable/12/usr.sbin/bhyve/pci_xhci.c 372444 2022-08-25 17:33:42Z jhb $");
37
38 #include <sys/param.h>
39 #include <sys/uio.h>
40 #include <sys/types.h>
41 #include <sys/queue.h>
42
43 #include <stdio.h>
44 #include <stdlib.h>
45 #include <stdint.h>
46 #include <string.h>
47 #include <errno.h>
48 #include <pthread.h>
49 #include <unistd.h>
50
51 #include <dev/usb/usbdi.h>
52 #include <dev/usb/usb.h>
53 #include <dev/usb/usb_freebsd.h>
54 #include <xhcireg.h>
55
56 #include "bhyverun.h"
57 #include "debug.h"
58 #include "pci_emul.h"
59 #include "pci_xhci.h"
60 #include "usb_emul.h"
61
62
63 static int xhci_debug = 0;
64 #define DPRINTF(params) if (xhci_debug) PRINTLN params
65 #define WPRINTF(params) PRINTLN params
66
67
68 #define XHCI_NAME "xhci"
69 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */
70
71 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */
72
73 /*
74 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping
75 * to 4k to avoid going over the guest physical memory barrier.
76 */
77 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */
78
79 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */
80
81 #define XHCI_CAPLEN (4*8) /* offset of op register space */
82 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */
83 #define XHCI_PORTREGS_START 0x400
84 #define XHCI_DOORBELL_MAX 256
85
86 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */
87
88 /* caplength and hci-version registers */
89 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF)
90 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16)
91 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF)
92
93 /* hcsparams1 register */
94 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF)
95 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8)
96 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24)
97
98 /* hcsparams2 register */
99 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F)
100 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4)
101 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21)
102 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27)
103
104 /* hcsparams3 register */
105 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF)
106 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16)
107
108 /* hccparams1 register */
109 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01)
110 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1)
111 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2)
112 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3)
113 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4)
114 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5)
115 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6)
116 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7)
117 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8)
118 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9)
119 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10)
120 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11)
121 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12)
122 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16)
123
124 /* hccparams2 register */
125 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01)
126 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1)
127 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2)
128 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3)
129 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4)
130 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5)
131
132 /* other registers */
133 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03)
134 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F)
135
136 /* register masks */
137 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */
138 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */
139 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */
140
141 /* port register set */
142 #define XHCI_PORTREGS_BASE 0x400 /* base offset */
143 #define XHCI_PORTREGS_PORT0 0x3F0
144 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */
145
146 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL)
147 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL)
148
149 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \
150 (((b) & (m)) << (s)))
151 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \
152 (((b) & ((m) << (s)))))
153
154 struct pci_xhci_trb_ring {
155 uint64_t ringaddr; /* current dequeue guest address */
156 uint32_t ccs; /* consumer cycle state */
157 };
158
159 /* device endpoint transfer/stream rings */
160 struct pci_xhci_dev_ep {
161 union {
162 struct xhci_trb *_epu_tr;
163 struct xhci_stream_ctx *_epu_sctx;
164 } _ep_trbsctx;
165 #define ep_tr _ep_trbsctx._epu_tr
166 #define ep_sctx _ep_trbsctx._epu_sctx
167
168 /*
169 * Caches the value of MaxPStreams from the endpoint context
170 * when an endpoint is initialized and is used to validate the
171 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length
172 * of ep_sctx_trbs[].
173 */
174 uint32_t ep_MaxPStreams;
175 union {
176 struct pci_xhci_trb_ring _epu_trb;
177 struct pci_xhci_trb_ring *_epu_sctx_trbs;
178 } _ep_trb_rings;
179 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr
180 #define ep_ccs _ep_trb_rings._epu_trb.ccs
181 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs
182
183 struct usb_data_xfer *ep_xfer; /* transfer chain */
184 };
185
186 /* device context base address array: maps slot->device context */
187 struct xhci_dcbaa {
188 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */
189 };
190
191 /* port status registers */
192 struct pci_xhci_portregs {
193 uint32_t portsc; /* port status and control */
194 uint32_t portpmsc; /* port pwr mgmt status & control */
195 uint32_t portli; /* port link info */
196 uint32_t porthlpmc; /* port hardware LPM control */
197 } __packed;
198 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10)
199
200 /* xHC operational registers */
201 struct pci_xhci_opregs {
202 uint32_t usbcmd; /* usb command */
203 uint32_t usbsts; /* usb status */
204 uint32_t pgsz; /* page size */
205 uint32_t dnctrl; /* device notification control */
206 uint64_t crcr; /* command ring control */
207 uint64_t dcbaap; /* device ctx base addr array ptr */
208 uint32_t config; /* configure */
209
210 /* guest mapped addresses: */
211 struct xhci_trb *cr_p; /* crcr dequeue */
212 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */
213 };
214
215 /* xHC runtime registers */
216 struct pci_xhci_rtsregs {
217 uint32_t mfindex; /* microframe index */
218 struct { /* interrupter register set */
219 uint32_t iman; /* interrupter management */
220 uint32_t imod; /* interrupter moderation */
221 uint32_t erstsz; /* event ring segment table size */
222 uint32_t rsvd;
223 uint64_t erstba; /* event ring seg-tbl base addr */
224 uint64_t erdp; /* event ring dequeue ptr */
225 } intrreg __packed;
226
227 /* guest mapped addresses */
228 struct xhci_event_ring_seg *erstba_p;
229 struct xhci_trb *erst_p; /* event ring segment tbl */
230 int er_deq_seg; /* event ring dequeue segment */
231 int er_enq_idx; /* event ring enqueue index - xHCI */
232 int er_enq_seg; /* event ring enqueue segment */
233 uint32_t er_events_cnt; /* number of events in ER */
234 uint32_t event_pcs; /* producer cycle state flag */
235 };
236
237
238 struct pci_xhci_softc;
239
240
241 /*
242 * USB device emulation container.
243 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each
244 * emulated device instance.
245 */
246 struct pci_xhci_dev_emu {
247 struct pci_xhci_softc *xsc;
248
249 /* XHCI contexts */
250 struct xhci_dev_ctx *dev_ctx;
251 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS];
252 int dev_slotstate;
253
254 struct usb_devemu *dev_ue; /* USB emulated dev */
255 void *dev_sc; /* device's softc */
256
257 struct usb_hci hci;
258 };
259
260 struct pci_xhci_softc {
261 struct pci_devinst *xsc_pi;
262
263 pthread_mutex_t mtx;
264
265 uint32_t caplength; /* caplen & hciversion */
266 uint32_t hcsparams1; /* structural parameters 1 */
267 uint32_t hcsparams2; /* structural parameters 2 */
268 uint32_t hcsparams3; /* structural parameters 3 */
269 uint32_t hccparams1; /* capability parameters 1 */
270 uint32_t dboff; /* doorbell offset */
271 uint32_t rtsoff; /* runtime register space offset */
272 uint32_t hccparams2; /* capability parameters 2 */
273
274 uint32_t regsend; /* end of configuration registers */
275
276 struct pci_xhci_opregs opregs;
277 struct pci_xhci_rtsregs rtsregs;
278
279 struct pci_xhci_portregs *portregs;
280 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */
281 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */
282 int ndevices;
283
284 int usb2_port_start;
285 int usb3_port_start;
286 };
287
288
289 /* portregs and devices arrays are set up to start from idx=1 */
290 #define XHCI_PORTREG_PTR(x,n) &(x)->portregs[(n)]
291 #define XHCI_DEVINST_PTR(x,n) (x)->devices[(n)]
292 #define XHCI_SLOTDEV_PTR(x,n) (x)->slots[(n)]
293
294 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH)
295
296 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \
297 (a), \
298 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1)))
299
300 static int xhci_in_use;
301
302 /* map USB errors to XHCI */
303 static const int xhci_usb_errors[USB_ERR_MAX] = {
304 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS,
305 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE,
306 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
307 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID,
308 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE,
309 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED,
310 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER,
311 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER,
312 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER,
313 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL,
314 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE,
315 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE,
316 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE,
317 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED,
318 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED,
319 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE,
320 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON,
321 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE,
322 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB,
323 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
324 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED,
325 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT,
326 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL,
327 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED,
328 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF,
329 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB,
330 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED,
331 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED,
332 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED,
333 };
334 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \
335 XHCI_TRB_ERROR_INVALID)
336
337 static int pci_xhci_insert_event(struct pci_xhci_softc *sc,
338 struct xhci_trb *evtrb, int do_intr);
339 static void pci_xhci_dump_trb(struct xhci_trb *trb);
340 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc);
341 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot);
342 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm);
343 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
344 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
345 struct xhci_endp_ctx *ep_ctx, uint32_t streamid,
346 uint64_t ringaddr, int ccs);
347
348 static void
pci_xhci_set_evtrb(struct xhci_trb * evtrb,uint64_t port,uint32_t errcode,uint32_t evtype)349 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode,
350 uint32_t evtype)
351 {
352 evtrb->qwTrb0 = port << 24;
353 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode);
354 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype);
355 }
356
357
358 /* controller reset */
359 static void
pci_xhci_reset(struct pci_xhci_softc * sc)360 pci_xhci_reset(struct pci_xhci_softc *sc)
361 {
362 int i;
363
364 sc->rtsregs.er_enq_idx = 0;
365 sc->rtsregs.er_events_cnt = 0;
366 sc->rtsregs.event_pcs = 1;
367
368 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
369 pci_xhci_reset_slot(sc, i);
370 }
371 }
372
373 static uint32_t
pci_xhci_usbcmd_write(struct pci_xhci_softc * sc,uint32_t cmd)374 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd)
375 {
376 int do_intr = 0;
377 int i;
378
379 if (cmd & XHCI_CMD_RS) {
380 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0;
381
382 sc->opregs.usbcmd |= XHCI_CMD_RS;
383 sc->opregs.usbsts &= ~XHCI_STS_HCH;
384 sc->opregs.usbsts |= XHCI_STS_PCD;
385
386 /* Queue port change event on controller run from stop */
387 if (do_intr)
388 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
389 struct pci_xhci_dev_emu *dev;
390 struct pci_xhci_portregs *port;
391 struct xhci_trb evtrb;
392
393 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL)
394 continue;
395
396 port = XHCI_PORTREG_PTR(sc, i);
397 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS;
398 port->portsc &= ~XHCI_PS_PLS_MASK;
399
400 /*
401 * XHCI 4.19.3 USB2 RxDetect->Polling,
402 * USB3 Polling->U0
403 */
404 if (dev->dev_ue->ue_usbver == 2)
405 port->portsc |=
406 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL);
407 else
408 port->portsc |=
409 XHCI_PS_PLS_SET(UPS_PORT_LS_U0);
410
411 pci_xhci_set_evtrb(&evtrb, i,
412 XHCI_TRB_ERROR_SUCCESS,
413 XHCI_TRB_EVENT_PORT_STS_CHANGE);
414
415 if (pci_xhci_insert_event(sc, &evtrb, 0) !=
416 XHCI_TRB_ERROR_SUCCESS)
417 break;
418 }
419 } else {
420 sc->opregs.usbcmd &= ~XHCI_CMD_RS;
421 sc->opregs.usbsts |= XHCI_STS_HCH;
422 sc->opregs.usbsts &= ~XHCI_STS_PCD;
423 }
424
425 /* start execution of schedule; stop when set to 0 */
426 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS;
427
428 if (cmd & XHCI_CMD_HCRST) {
429 /* reset controller */
430 pci_xhci_reset(sc);
431 cmd &= ~XHCI_CMD_HCRST;
432 }
433
434 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS);
435
436 if (do_intr)
437 pci_xhci_assert_interrupt(sc);
438
439 return (cmd);
440 }
441
442 static void
pci_xhci_portregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)443 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
444 uint64_t value)
445 {
446 struct xhci_trb evtrb;
447 struct pci_xhci_portregs *p;
448 int port;
449 uint32_t oldpls, newpls;
450
451 if (sc->portregs == NULL)
452 return;
453
454 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
455 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
456
457 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx",
458 offset, port, value));
459
460 assert(port >= 0);
461
462 if (port > XHCI_MAX_DEVS) {
463 DPRINTF(("pci_xhci: portregs_write port %d > ndevices",
464 port));
465 return;
466 }
467
468 if (XHCI_DEVINST_PTR(sc, port) == NULL) {
469 DPRINTF(("pci_xhci: portregs_write to unattached port %d",
470 port));
471 }
472
473 p = XHCI_PORTREG_PTR(sc, port);
474 switch (offset) {
475 case 0:
476 /* port reset or warm reset */
477 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) {
478 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR);
479 break;
480 }
481
482 if ((p->portsc & XHCI_PS_PP) == 0) {
483 WPRINTF(("pci_xhci: portregs_write to unpowered "
484 "port %d", port));
485 break;
486 }
487
488 /* Port status and control register */
489 oldpls = XHCI_PS_PLS_GET(p->portsc);
490 newpls = XHCI_PS_PLS_GET(value);
491
492 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
493 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
494
495 if (XHCI_DEVINST_PTR(sc, port))
496 p->portsc |= XHCI_PS_CCS;
497
498 p->portsc |= (value &
499 ~(XHCI_PS_OCA |
500 XHCI_PS_PR |
501 XHCI_PS_PED |
502 XHCI_PS_PLS_MASK | /* link state */
503 XHCI_PS_SPEED_MASK |
504 XHCI_PS_PIC_MASK | /* port indicator */
505 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR));
506
507 /* clear control bits */
508 p->portsc &= ~(value &
509 (XHCI_PS_CSC |
510 XHCI_PS_PEC |
511 XHCI_PS_WRC |
512 XHCI_PS_OCC |
513 XHCI_PS_PRC |
514 XHCI_PS_PLC |
515 XHCI_PS_CEC |
516 XHCI_PS_CAS));
517
518 /* port disable request; for USB3, don't care */
519 if (value & XHCI_PS_PED)
520 DPRINTF(("Disable port %d request", port));
521
522 if (!(value & XHCI_PS_LWS))
523 break;
524
525 DPRINTF(("Port new PLS: %d", newpls));
526 switch (newpls) {
527 case 0: /* U0 */
528 case 3: /* U3 */
529 if (oldpls != newpls) {
530 p->portsc &= ~XHCI_PS_PLS_MASK;
531 p->portsc |= XHCI_PS_PLS_SET(newpls) |
532 XHCI_PS_PLC;
533
534 if (oldpls != 0 && newpls == 0) {
535 pci_xhci_set_evtrb(&evtrb, port,
536 XHCI_TRB_ERROR_SUCCESS,
537 XHCI_TRB_EVENT_PORT_STS_CHANGE);
538
539 pci_xhci_insert_event(sc, &evtrb, 1);
540 }
541 }
542 break;
543
544 default:
545 DPRINTF(("Unhandled change port %d PLS %u",
546 port, newpls));
547 break;
548 }
549 break;
550 case 4:
551 /* Port power management status and control register */
552 p->portpmsc = value;
553 break;
554 case 8:
555 /* Port link information register */
556 DPRINTF(("pci_xhci attempted write to PORTLI, port %d",
557 port));
558 break;
559 case 12:
560 /*
561 * Port hardware LPM control register.
562 * For USB3, this register is reserved.
563 */
564 p->porthlpmc = value;
565 break;
566 }
567 }
568
569 struct xhci_dev_ctx *
pci_xhci_get_dev_ctx(struct pci_xhci_softc * sc,uint32_t slot)570 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot)
571 {
572 uint64_t devctx_addr;
573 struct xhci_dev_ctx *devctx;
574
575 assert(slot > 0 && slot <= sc->ndevices);
576 assert(sc->opregs.dcbaa_p != NULL);
577
578 devctx_addr = sc->opregs.dcbaa_p->dcba[slot];
579
580 if (devctx_addr == 0) {
581 DPRINTF(("get_dev_ctx devctx_addr == 0"));
582 return (NULL);
583 }
584
585 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx",
586 slot, devctx_addr));
587 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL);
588
589 return (devctx);
590 }
591
592 struct xhci_trb *
pci_xhci_trb_next(struct pci_xhci_softc * sc,struct xhci_trb * curtrb,uint64_t * guestaddr)593 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb,
594 uint64_t *guestaddr)
595 {
596 struct xhci_trb *next;
597
598 assert(curtrb != NULL);
599
600 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
601 if (guestaddr)
602 *guestaddr = curtrb->qwTrb0 & ~0xFUL;
603
604 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
605 } else {
606 if (guestaddr)
607 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL;
608
609 next = curtrb + 1;
610 }
611
612 return (next);
613 }
614
615 static void
pci_xhci_assert_interrupt(struct pci_xhci_softc * sc)616 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc)
617 {
618
619 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY;
620 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND;
621 sc->opregs.usbsts |= XHCI_STS_EINT;
622
623 /* only trigger interrupt if permitted */
624 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) &&
625 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) {
626 if (pci_msi_enabled(sc->xsc_pi))
627 pci_generate_msi(sc->xsc_pi, 0);
628 else
629 pci_lintr_assert(sc->xsc_pi);
630 }
631 }
632
633 static void
pci_xhci_deassert_interrupt(struct pci_xhci_softc * sc)634 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc)
635 {
636
637 if (!pci_msi_enabled(sc->xsc_pi))
638 pci_lintr_assert(sc->xsc_pi);
639 }
640
641 static void
pci_xhci_init_ep(struct pci_xhci_dev_emu * dev,int epid)642 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid)
643 {
644 struct xhci_dev_ctx *dev_ctx;
645 struct pci_xhci_dev_ep *devep;
646 struct xhci_endp_ctx *ep_ctx;
647 uint32_t pstreams;
648 int i;
649
650 dev_ctx = dev->dev_ctx;
651 ep_ctx = &dev_ctx->ctx_ep[epid];
652 devep = &dev->eps[epid];
653 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0);
654 if (pstreams > 0) {
655 DPRINTF(("init_ep %d with pstreams %d", epid, pstreams));
656 assert(devep->ep_sctx_trbs == NULL);
657
658 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 &
659 XHCI_EPCTX_2_TR_DQ_PTR_MASK);
660 devep->ep_sctx_trbs = calloc(pstreams,
661 sizeof(struct pci_xhci_trb_ring));
662 for (i = 0; i < pstreams; i++) {
663 devep->ep_sctx_trbs[i].ringaddr =
664 devep->ep_sctx[i].qwSctx0 &
665 XHCI_SCTX_0_TR_DQ_PTR_MASK;
666 devep->ep_sctx_trbs[i].ccs =
667 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0);
668 }
669 } else {
670 DPRINTF(("init_ep %d with no pstreams", epid));
671 devep->ep_ringaddr = ep_ctx->qwEpCtx2 &
672 XHCI_EPCTX_2_TR_DQ_PTR_MASK;
673 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2);
674 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr);
675 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs));
676 }
677 devep->ep_MaxPStreams = pstreams;
678
679 if (devep->ep_xfer == NULL) {
680 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer));
681 USB_DATA_XFER_INIT(devep->ep_xfer);
682 }
683 }
684
685 static void
pci_xhci_disable_ep(struct pci_xhci_dev_emu * dev,int epid)686 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid)
687 {
688 struct xhci_dev_ctx *dev_ctx;
689 struct pci_xhci_dev_ep *devep;
690 struct xhci_endp_ctx *ep_ctx;
691
692 DPRINTF(("pci_xhci disable_ep %d", epid));
693
694 dev_ctx = dev->dev_ctx;
695 ep_ctx = &dev_ctx->ctx_ep[epid];
696 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED;
697
698 devep = &dev->eps[epid];
699 if (devep->ep_MaxPStreams > 0)
700 free(devep->ep_sctx_trbs);
701
702 if (devep->ep_xfer != NULL) {
703 free(devep->ep_xfer);
704 devep->ep_xfer = NULL;
705 }
706
707 memset(devep, 0, sizeof(struct pci_xhci_dev_ep));
708 }
709
710
711 /* reset device at slot and data structures related to it */
712 static void
pci_xhci_reset_slot(struct pci_xhci_softc * sc,int slot)713 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot)
714 {
715 struct pci_xhci_dev_emu *dev;
716
717 dev = XHCI_SLOTDEV_PTR(sc, slot);
718
719 if (!dev) {
720 DPRINTF(("xhci reset unassigned slot (%d)?", slot));
721 } else {
722 dev->dev_slotstate = XHCI_ST_DISABLED;
723 }
724
725 /* TODO: reset ring buffer pointers */
726 }
727
728 static int
pci_xhci_insert_event(struct pci_xhci_softc * sc,struct xhci_trb * evtrb,int do_intr)729 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb,
730 int do_intr)
731 {
732 struct pci_xhci_rtsregs *rts;
733 uint64_t erdp;
734 int erdp_idx;
735 int err;
736 struct xhci_trb *evtrbptr;
737
738 err = XHCI_TRB_ERROR_SUCCESS;
739
740 rts = &sc->rtsregs;
741
742 erdp = rts->intrreg.erdp & ~0xF;
743 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) /
744 sizeof(struct xhci_trb);
745
746 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]",
747 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));
748 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u",
749 erdp_idx, rts->er_deq_seg, rts->er_enq_idx,
750 rts->er_enq_seg, rts->event_pcs));
751 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)",
752 erdp, rts->erstba_p->qwEvrsTablePtr,
753 rts->erstba_p->dwEvrsTableSize, do_intr));
754
755 evtrbptr = &rts->erst_p[rts->er_enq_idx];
756
757 /* TODO: multi-segment table */
758 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) {
759 DPRINTF(("pci_xhci[%d] cannot insert event; ring full",
760 __LINE__));
761 err = XHCI_TRB_ERROR_EV_RING_FULL;
762 goto done;
763 }
764
765 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) {
766 struct xhci_trb errev;
767
768 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) {
769
770 DPRINTF(("pci_xhci[%d] insert evt err: ring full",
771 __LINE__));
772
773 errev.qwTrb0 = 0;
774 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET(
775 XHCI_TRB_ERROR_EV_RING_FULL);
776 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET(
777 XHCI_TRB_EVENT_HOST_CTRL) |
778 rts->event_pcs;
779 rts->er_events_cnt++;
780 memcpy(&rts->erst_p[rts->er_enq_idx], &errev,
781 sizeof(struct xhci_trb));
782 rts->er_enq_idx = (rts->er_enq_idx + 1) %
783 rts->erstba_p->dwEvrsTableSize;
784 err = XHCI_TRB_ERROR_EV_RING_FULL;
785 do_intr = 1;
786
787 goto done;
788 }
789 } else {
790 rts->er_events_cnt++;
791 }
792
793 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT;
794 evtrb->dwTrb3 |= rts->event_pcs;
795
796 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb));
797 rts->er_enq_idx = (rts->er_enq_idx + 1) %
798 rts->erstba_p->dwEvrsTableSize;
799
800 if (rts->er_enq_idx == 0)
801 rts->event_pcs ^= 1;
802
803 done:
804 if (do_intr)
805 pci_xhci_assert_interrupt(sc);
806
807 return (err);
808 }
809
810 static uint32_t
pci_xhci_cmd_enable_slot(struct pci_xhci_softc * sc,uint32_t * slot)811 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot)
812 {
813 struct pci_xhci_dev_emu *dev;
814 uint32_t cmderr;
815 int i;
816
817 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
818 if (sc->portregs != NULL)
819 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
820 dev = XHCI_SLOTDEV_PTR(sc, i);
821 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) {
822 *slot = i;
823 dev->dev_slotstate = XHCI_ST_ENABLED;
824 cmderr = XHCI_TRB_ERROR_SUCCESS;
825 dev->hci.hci_address = i;
826 break;
827 }
828 }
829
830 DPRINTF(("pci_xhci enable slot (error=%d) slot %u",
831 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot));
832
833 return (cmderr);
834 }
835
836 static uint32_t
pci_xhci_cmd_disable_slot(struct pci_xhci_softc * sc,uint32_t slot)837 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot)
838 {
839 struct pci_xhci_dev_emu *dev;
840 uint32_t cmderr;
841
842 DPRINTF(("pci_xhci disable slot %u", slot));
843
844 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
845 if (sc->portregs == NULL)
846 goto done;
847
848 if (slot > sc->ndevices) {
849 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
850 goto done;
851 }
852
853 dev = XHCI_SLOTDEV_PTR(sc, slot);
854 if (dev) {
855 if (dev->dev_slotstate == XHCI_ST_DISABLED) {
856 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
857 } else {
858 dev->dev_slotstate = XHCI_ST_DISABLED;
859 cmderr = XHCI_TRB_ERROR_SUCCESS;
860 /* TODO: reset events and endpoints */
861 }
862 }
863
864 done:
865 return (cmderr);
866 }
867
868 static uint32_t
pci_xhci_cmd_reset_device(struct pci_xhci_softc * sc,uint32_t slot)869 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot)
870 {
871 struct pci_xhci_dev_emu *dev;
872 struct xhci_dev_ctx *dev_ctx;
873 struct xhci_endp_ctx *ep_ctx;
874 uint32_t cmderr;
875 int i;
876
877 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
878 if (sc->portregs == NULL)
879 goto done;
880
881 DPRINTF(("pci_xhci reset device slot %u", slot));
882
883 dev = XHCI_SLOTDEV_PTR(sc, slot);
884 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED)
885 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
886 else {
887 dev->dev_slotstate = XHCI_ST_DEFAULT;
888
889 dev->hci.hci_address = 0;
890 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
891
892 /* slot state */
893 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
894 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT,
895 0x1F, 27);
896
897 /* number of contexts */
898 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
899 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
900
901 /* reset all eps other than ep-0 */
902 for (i = 2; i <= 31; i++) {
903 ep_ctx = &dev_ctx->ctx_ep[i];
904 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0,
905 XHCI_ST_EPCTX_DISABLED, 0x7, 0);
906 }
907
908 cmderr = XHCI_TRB_ERROR_SUCCESS;
909 }
910
911 pci_xhci_reset_slot(sc, slot);
912
913 done:
914 return (cmderr);
915 }
916
917 static uint32_t
pci_xhci_cmd_address_device(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)918 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot,
919 struct xhci_trb *trb)
920 {
921 struct pci_xhci_dev_emu *dev;
922 struct xhci_input_dev_ctx *input_ctx;
923 struct xhci_slot_ctx *islot_ctx;
924 struct xhci_dev_ctx *dev_ctx;
925 struct xhci_endp_ctx *ep0_ctx;
926 uint32_t cmderr;
927
928 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
929 islot_ctx = &input_ctx->ctx_slot;
930 ep0_ctx = &input_ctx->ctx_ep[1];
931
932 cmderr = XHCI_TRB_ERROR_SUCCESS;
933
934 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,",
935 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
936 DPRINTF((" slot %08x %08x %08x %08x",
937 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
938 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
939 DPRINTF((" ep0 %08x %08x %016lx %08x",
940 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
941 ep0_ctx->dwEpCtx4));
942
943 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */
944 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
945 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) {
946 DPRINTF(("pci_xhci: address device, input ctl invalid"));
947 cmderr = XHCI_TRB_ERROR_TRB;
948 goto done;
949 }
950
951 /* assign address to slot */
952 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
953
954 DPRINTF(("pci_xhci: address device, dev ctx"));
955 DPRINTF((" slot %08x %08x %08x %08x",
956 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
957 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
958
959 dev = XHCI_SLOTDEV_PTR(sc, slot);
960 assert(dev != NULL);
961
962 dev->hci.hci_address = slot;
963 dev->dev_ctx = dev_ctx;
964
965 if (dev->dev_ue->ue_reset == NULL ||
966 dev->dev_ue->ue_reset(dev->dev_sc) < 0) {
967 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
968 goto done;
969 }
970
971 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx));
972
973 dev_ctx->ctx_slot.dwSctx3 =
974 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) |
975 XHCI_SCTX_3_DEV_ADDR_SET(slot);
976
977 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx));
978 ep0_ctx = &dev_ctx->ctx_ep[1];
979 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) |
980 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING);
981
982 pci_xhci_init_ep(dev, 1);
983
984 dev->dev_slotstate = XHCI_ST_ADDRESSED;
985
986 DPRINTF(("pci_xhci: address device, output ctx"));
987 DPRINTF((" slot %08x %08x %08x %08x",
988 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
989 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
990 DPRINTF((" ep0 %08x %08x %016lx %08x",
991 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
992 ep0_ctx->dwEpCtx4));
993
994 done:
995 return (cmderr);
996 }
997
998 static uint32_t
pci_xhci_cmd_config_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)999 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot,
1000 struct xhci_trb *trb)
1001 {
1002 struct xhci_input_dev_ctx *input_ctx;
1003 struct pci_xhci_dev_emu *dev;
1004 struct xhci_dev_ctx *dev_ctx;
1005 struct xhci_endp_ctx *ep_ctx, *iep_ctx;
1006 uint32_t cmderr;
1007 int i;
1008
1009 cmderr = XHCI_TRB_ERROR_SUCCESS;
1010
1011 DPRINTF(("pci_xhci config_ep slot %u", slot));
1012
1013 dev = XHCI_SLOTDEV_PTR(sc, slot);
1014 assert(dev != NULL);
1015
1016 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) {
1017 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u",
1018 slot));
1019 if (dev->dev_ue->ue_stop != NULL)
1020 dev->dev_ue->ue_stop(dev->dev_sc);
1021
1022 dev->dev_slotstate = XHCI_ST_ADDRESSED;
1023
1024 dev->hci.hci_address = 0;
1025 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1026
1027 /* number of contexts */
1028 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
1029 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
1030
1031 /* slot state */
1032 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1033 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED,
1034 0x1F, 27);
1035
1036 /* disable endpoints */
1037 for (i = 2; i < 32; i++)
1038 pci_xhci_disable_ep(dev, i);
1039
1040 cmderr = XHCI_TRB_ERROR_SUCCESS;
1041
1042 goto done;
1043 }
1044
1045 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) {
1046 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed",
1047 dev->dev_slotstate));
1048 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
1049 goto done;
1050 }
1051
1052 /* In addressed/configured state;
1053 * for each drop endpoint ctx flag:
1054 * ep->state = DISABLED
1055 * for each add endpoint ctx flag:
1056 * cp(ep-in, ep-out)
1057 * ep->state = RUNNING
1058 * for each drop+add endpoint flag:
1059 * reset ep resources
1060 * cp(ep-in, ep-out)
1061 * ep->state = RUNNING
1062 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled)
1063 * slot->state = configured
1064 */
1065
1066 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1067 dev_ctx = dev->dev_ctx;
1068 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x",
1069 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1,
1070 input_ctx->ctx_input.dwInCtx7));
1071
1072 for (i = 2; i <= 31; i++) {
1073 ep_ctx = &dev_ctx->ctx_ep[i];
1074
1075 if (input_ctx->ctx_input.dwInCtx0 &
1076 XHCI_INCTX_0_DROP_MASK(i)) {
1077 DPRINTF((" config ep - dropping ep %d", i));
1078 pci_xhci_disable_ep(dev, i);
1079 }
1080
1081 if (input_ctx->ctx_input.dwInCtx1 &
1082 XHCI_INCTX_1_ADD_MASK(i)) {
1083 iep_ctx = &input_ctx->ctx_ep[i];
1084
1085 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x",
1086 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1,
1087 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4));
1088
1089 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx));
1090
1091 pci_xhci_init_ep(dev, i);
1092
1093 /* ep state */
1094 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1095 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1096 }
1097 }
1098
1099 /* slot state to configured */
1100 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1101 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27);
1102 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY(
1103 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27);
1104 dev->dev_slotstate = XHCI_ST_CONFIGURED;
1105
1106 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x "
1107 "[3]=0x%08x",
1108 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1109 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1110
1111 done:
1112 return (cmderr);
1113 }
1114
1115 static uint32_t
pci_xhci_cmd_reset_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1116 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot,
1117 struct xhci_trb *trb)
1118 {
1119 struct pci_xhci_dev_emu *dev;
1120 struct pci_xhci_dev_ep *devep;
1121 struct xhci_dev_ctx *dev_ctx;
1122 struct xhci_endp_ctx *ep_ctx;
1123 uint32_t cmderr, epid;
1124 uint32_t type;
1125
1126 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1127
1128 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot));
1129
1130 cmderr = XHCI_TRB_ERROR_SUCCESS;
1131
1132 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1133
1134 dev = XHCI_SLOTDEV_PTR(sc, slot);
1135 assert(dev != NULL);
1136
1137 if (type == XHCI_TRB_TYPE_STOP_EP &&
1138 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) {
1139 /* XXX suspend endpoint for 10ms */
1140 }
1141
1142 if (epid < 1 || epid > 31) {
1143 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid));
1144 cmderr = XHCI_TRB_ERROR_TRB;
1145 goto done;
1146 }
1147
1148 devep = &dev->eps[epid];
1149 if (devep->ep_xfer != NULL)
1150 USB_DATA_XFER_RESET(devep->ep_xfer);
1151
1152 dev_ctx = dev->dev_ctx;
1153 assert(dev_ctx != NULL);
1154
1155 ep_ctx = &dev_ctx->ctx_ep[epid];
1156
1157 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1158
1159 if (devep->ep_MaxPStreams == 0)
1160 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs;
1161
1162 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x",
1163 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1164 ep_ctx->dwEpCtx4));
1165
1166 if (type == XHCI_TRB_TYPE_RESET_EP &&
1167 (dev->dev_ue->ue_reset == NULL ||
1168 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) {
1169 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
1170 goto done;
1171 }
1172
1173 done:
1174 return (cmderr);
1175 }
1176
1177
1178 static uint32_t
pci_xhci_find_stream(struct pci_xhci_softc * sc,struct xhci_endp_ctx * ep,struct pci_xhci_dev_ep * devep,uint32_t streamid,struct xhci_stream_ctx ** osctx)1179 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep,
1180 struct pci_xhci_dev_ep *devep, uint32_t streamid,
1181 struct xhci_stream_ctx **osctx)
1182 {
1183 struct xhci_stream_ctx *sctx;
1184
1185 if (devep->ep_MaxPStreams == 0)
1186 return (XHCI_TRB_ERROR_TRB);
1187
1188 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX)
1189 return (XHCI_TRB_ERROR_INVALID_SID);
1190
1191 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) {
1192 DPRINTF(("pci_xhci: find_stream; LSA bit not set"));
1193 return (XHCI_TRB_ERROR_INVALID_SID);
1194 }
1195
1196 /* only support primary stream */
1197 if (streamid > devep->ep_MaxPStreams)
1198 return (XHCI_TRB_ERROR_STREAM_TYPE);
1199
1200 sctx = XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) + streamid;
1201 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0))
1202 return (XHCI_TRB_ERROR_STREAM_TYPE);
1203
1204 *osctx = sctx;
1205
1206 return (XHCI_TRB_ERROR_SUCCESS);
1207 }
1208
1209
1210 static uint32_t
pci_xhci_cmd_set_tr(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1211 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot,
1212 struct xhci_trb *trb)
1213 {
1214 struct pci_xhci_dev_emu *dev;
1215 struct pci_xhci_dev_ep *devep;
1216 struct xhci_dev_ctx *dev_ctx;
1217 struct xhci_endp_ctx *ep_ctx;
1218 uint32_t cmderr, epid;
1219 uint32_t streamid;
1220
1221 cmderr = XHCI_TRB_ERROR_SUCCESS;
1222
1223 dev = XHCI_SLOTDEV_PTR(sc, slot);
1224 assert(dev != NULL);
1225
1226 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u",
1227 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7),
1228 (uint32_t)(trb->qwTrb0 & 0x1)));
1229 DPRINTF((" stream-id %u, slot %u, epid %u, C %u",
1230 (trb->dwTrb2 >> 16) & 0xFFFF,
1231 XHCI_TRB_3_SLOT_GET(trb->dwTrb3),
1232 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1));
1233
1234 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1235 if (epid < 1 || epid > 31) {
1236 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid));
1237 cmderr = XHCI_TRB_ERROR_TRB;
1238 goto done;
1239 }
1240
1241 dev_ctx = dev->dev_ctx;
1242 assert(dev_ctx != NULL);
1243
1244 ep_ctx = &dev_ctx->ctx_ep[epid];
1245 devep = &dev->eps[epid];
1246
1247 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) {
1248 case XHCI_ST_EPCTX_STOPPED:
1249 case XHCI_ST_EPCTX_ERROR:
1250 break;
1251 default:
1252 DPRINTF(("pci_xhci cmd set_tr invalid state %x",
1253 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)));
1254 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE;
1255 goto done;
1256 }
1257
1258 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2);
1259 if (devep->ep_MaxPStreams > 0) {
1260 struct xhci_stream_ctx *sctx;
1261
1262 sctx = NULL;
1263 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid,
1264 &sctx);
1265 if (sctx != NULL) {
1266 assert(devep->ep_sctx != NULL);
1267
1268 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
1269 devep->ep_sctx_trbs[streamid].ringaddr =
1270 trb->qwTrb0 & ~0xF;
1271 devep->ep_sctx_trbs[streamid].ccs =
1272 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0);
1273 }
1274 } else {
1275 if (streamid != 0) {
1276 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0",
1277 streamid));
1278 }
1279 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL;
1280 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL;
1281 devep->ep_ccs = trb->qwTrb0 & 0x1;
1282 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr);
1283
1284 DPRINTF(("pci_xhci set_tr first TRB:"));
1285 pci_xhci_dump_trb(devep->ep_tr);
1286 }
1287 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1288
1289 done:
1290 return (cmderr);
1291 }
1292
1293 static uint32_t
pci_xhci_cmd_eval_ctx(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1294 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot,
1295 struct xhci_trb *trb)
1296 {
1297 struct xhci_input_dev_ctx *input_ctx;
1298 struct xhci_slot_ctx *islot_ctx;
1299 struct xhci_dev_ctx *dev_ctx;
1300 struct xhci_endp_ctx *ep0_ctx;
1301 uint32_t cmderr;
1302
1303 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1304 islot_ctx = &input_ctx->ctx_slot;
1305 ep0_ctx = &input_ctx->ctx_ep[1];
1306
1307 cmderr = XHCI_TRB_ERROR_SUCCESS;
1308 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,",
1309 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
1310 DPRINTF((" slot %08x %08x %08x %08x",
1311 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
1312 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
1313 DPRINTF((" ep0 %08x %08x %016lx %08x",
1314 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1315 ep0_ctx->dwEpCtx4));
1316
1317 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */
1318 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
1319 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) {
1320 DPRINTF(("pci_xhci: eval ctx, input ctl invalid"));
1321 cmderr = XHCI_TRB_ERROR_TRB;
1322 goto done;
1323 }
1324
1325 /* assign address to slot; in this emulation, slot_id = address */
1326 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1327
1328 DPRINTF(("pci_xhci: eval ctx, dev ctx"));
1329 DPRINTF((" slot %08x %08x %08x %08x",
1330 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1331 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1332
1333 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */
1334 /* set max exit latency */
1335 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY(
1336 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1,
1337 0xFFFF, 0);
1338
1339 /* set interrupter target */
1340 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY(
1341 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2,
1342 0x3FF, 22);
1343 }
1344 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */
1345 /* set max packet size */
1346 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY(
1347 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1,
1348 0xFFFF, 16);
1349
1350 ep0_ctx = &dev_ctx->ctx_ep[1];
1351 }
1352
1353 DPRINTF(("pci_xhci: eval ctx, output ctx"));
1354 DPRINTF((" slot %08x %08x %08x %08x",
1355 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1356 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1357 DPRINTF((" ep0 %08x %08x %016lx %08x",
1358 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1359 ep0_ctx->dwEpCtx4));
1360
1361 done:
1362 return (cmderr);
1363 }
1364
1365 static int
pci_xhci_complete_commands(struct pci_xhci_softc * sc)1366 pci_xhci_complete_commands(struct pci_xhci_softc *sc)
1367 {
1368 struct xhci_trb evtrb;
1369 struct xhci_trb *trb;
1370 uint64_t crcr;
1371 uint32_t ccs; /* cycle state (XHCI 4.9.2) */
1372 uint32_t type;
1373 uint32_t slot;
1374 uint32_t cmderr;
1375 int error;
1376
1377 error = 0;
1378 sc->opregs.crcr |= XHCI_CRCR_LO_CRR;
1379
1380 trb = sc->opregs.cr_p;
1381 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS;
1382 crcr = sc->opregs.crcr & ~0xF;
1383
1384 while (1) {
1385 sc->opregs.cr_p = trb;
1386
1387 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1388
1389 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
1390 (ccs & XHCI_TRB_3_CYCLE_BIT))
1391 break;
1392
1393 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x"
1394 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u",
1395 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,
1396 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs));
1397
1398 cmderr = XHCI_TRB_ERROR_SUCCESS;
1399 evtrb.dwTrb2 = 0;
1400 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) |
1401 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE);
1402 slot = 0;
1403
1404 switch (type) {
1405 case XHCI_TRB_TYPE_LINK: /* 0x06 */
1406 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1407 ccs ^= XHCI_CRCR_LO_RCS;
1408 break;
1409
1410 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */
1411 cmderr = pci_xhci_cmd_enable_slot(sc, &slot);
1412 break;
1413
1414 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */
1415 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1416 cmderr = pci_xhci_cmd_disable_slot(sc, slot);
1417 break;
1418
1419 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */
1420 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1421 cmderr = pci_xhci_cmd_address_device(sc, slot, trb);
1422 break;
1423
1424 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */
1425 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1426 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb);
1427 break;
1428
1429 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */
1430 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1431 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb);
1432 break;
1433
1434 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */
1435 DPRINTF(("Reset Endpoint on slot %d", slot));
1436 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1437 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1438 break;
1439
1440 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */
1441 DPRINTF(("Stop Endpoint on slot %d", slot));
1442 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1443 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1444 break;
1445
1446 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */
1447 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1448 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb);
1449 break;
1450
1451 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */
1452 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1453 cmderr = pci_xhci_cmd_reset_device(sc, slot);
1454 break;
1455
1456 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */
1457 /* TODO: */
1458 break;
1459
1460 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */
1461 break;
1462
1463 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */
1464 break;
1465
1466 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */
1467 break;
1468
1469 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */
1470 break;
1471
1472 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */
1473 break;
1474
1475 default:
1476 DPRINTF(("pci_xhci: unsupported cmd %x", type));
1477 break;
1478 }
1479
1480 if (type != XHCI_TRB_TYPE_LINK) {
1481 /*
1482 * insert command completion event and assert intr
1483 */
1484 evtrb.qwTrb0 = crcr;
1485 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr);
1486 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot);
1487 DPRINTF(("pci_xhci: command 0x%x result: 0x%x",
1488 type, cmderr));
1489 pci_xhci_insert_event(sc, &evtrb, 1);
1490 }
1491
1492 trb = pci_xhci_trb_next(sc, trb, &crcr);
1493 }
1494
1495 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs;
1496 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR;
1497 return (error);
1498 }
1499
1500 static void
pci_xhci_dump_trb(struct xhci_trb * trb)1501 pci_xhci_dump_trb(struct xhci_trb *trb)
1502 {
1503 static const char *trbtypes[] = {
1504 "RESERVED",
1505 "NORMAL",
1506 "SETUP_STAGE",
1507 "DATA_STAGE",
1508 "STATUS_STAGE",
1509 "ISOCH",
1510 "LINK",
1511 "EVENT_DATA",
1512 "NOOP",
1513 "ENABLE_SLOT",
1514 "DISABLE_SLOT",
1515 "ADDRESS_DEVICE",
1516 "CONFIGURE_EP",
1517 "EVALUATE_CTX",
1518 "RESET_EP",
1519 "STOP_EP",
1520 "SET_TR_DEQUEUE",
1521 "RESET_DEVICE",
1522 "FORCE_EVENT",
1523 "NEGOTIATE_BW",
1524 "SET_LATENCY_TOL",
1525 "GET_PORT_BW",
1526 "FORCE_HEADER",
1527 "NOOP_CMD"
1528 };
1529 uint32_t type;
1530
1531 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1532 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x",
1533 trb, type,
1534 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID",
1535 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));
1536 }
1537
1538 static int
pci_xhci_xfer_complete(struct pci_xhci_softc * sc,struct usb_data_xfer * xfer,uint32_t slot,uint32_t epid,int * do_intr)1539 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer,
1540 uint32_t slot, uint32_t epid, int *do_intr)
1541 {
1542 struct pci_xhci_dev_emu *dev;
1543 struct pci_xhci_dev_ep *devep;
1544 struct xhci_dev_ctx *dev_ctx;
1545 struct xhci_endp_ctx *ep_ctx;
1546 struct xhci_trb *trb;
1547 struct xhci_trb evtrb;
1548 uint32_t trbflags;
1549 uint32_t edtla;
1550 int i, err;
1551
1552 dev = XHCI_SLOTDEV_PTR(sc, slot);
1553 devep = &dev->eps[epid];
1554 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1555
1556 assert(dev_ctx != NULL);
1557
1558 ep_ctx = &dev_ctx->ctx_ep[epid];
1559
1560 err = XHCI_TRB_ERROR_SUCCESS;
1561 *do_intr = 0;
1562 edtla = 0;
1563
1564 /* go through list of TRBs and insert event(s) */
1565 for (i = xfer->head; xfer->ndata > 0; ) {
1566 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data;
1567 trb = XHCI_GADDR(sc, evtrb.qwTrb0);
1568 trbflags = trb->dwTrb3;
1569
1570 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x "
1571 "(err %d) IOC?%d",
1572 i, xfer->data[i].processed, xfer->data[i].blen,
1573 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0,
1574 trbflags, err,
1575 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0));
1576
1577 if (!xfer->data[i].processed) {
1578 xfer->head = i;
1579 break;
1580 }
1581
1582 xfer->ndata--;
1583 edtla += xfer->data[i].bdone;
1584
1585 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs);
1586
1587 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx,
1588 xfer->data[i].streamid, xfer->data[i].trbnext,
1589 xfer->data[i].ccs);
1590
1591 /* Only interrupt if IOC or short packet */
1592 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) &&
1593 !((err == XHCI_TRB_ERROR_SHORT_PKT) &&
1594 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) {
1595
1596 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1597 continue;
1598 }
1599
1600 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) |
1601 XHCI_TRB_2_REM_SET(xfer->data[i].blen);
1602
1603 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) |
1604 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid);
1605
1606 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
1607 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
1608 evtrb.qwTrb0 = trb->qwTrb0;
1609 evtrb.dwTrb2 = (edtla & 0xFFFFF) |
1610 XHCI_TRB_2_ERROR_SET(err);
1611 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
1612 edtla = 0;
1613 }
1614
1615 *do_intr = 1;
1616
1617 err = pci_xhci_insert_event(sc, &evtrb, 0);
1618 if (err != XHCI_TRB_ERROR_SUCCESS) {
1619 break;
1620 }
1621
1622 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1623 }
1624
1625 return (err);
1626 }
1627
1628 static void
pci_xhci_update_ep_ring(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t streamid,uint64_t ringaddr,int ccs)1629 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, struct pci_xhci_dev_emu *dev,
1630 struct pci_xhci_dev_ep *devep, struct xhci_endp_ctx *ep_ctx,
1631 uint32_t streamid, uint64_t ringaddr, int ccs)
1632 {
1633
1634 if (devep->ep_MaxPStreams != 0) {
1635 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) |
1636 (ccs & 0x1);
1637
1638 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL;
1639 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1;
1640 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1);
1641
1642 DPRINTF(("xhci update ep-ring stream %d, addr %lx",
1643 streamid, devep->ep_sctx[streamid].qwSctx0));
1644 } else {
1645 devep->ep_ringaddr = ringaddr & ~0xFUL;
1646 devep->ep_ccs = ccs & 0x1;
1647 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL);
1648 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1);
1649
1650 DPRINTF(("xhci update ep-ring, addr %lx",
1651 (devep->ep_ringaddr | devep->ep_ccs)));
1652 }
1653 }
1654
1655 /*
1656 * Outstanding transfer still in progress (device NAK'd earlier) so retry
1657 * the transfer again to see if it succeeds.
1658 */
1659 static int
pci_xhci_try_usb_xfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t slot,uint32_t epid)1660 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc,
1661 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1662 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid)
1663 {
1664 struct usb_data_xfer *xfer;
1665 int err;
1666 int do_intr;
1667
1668 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1669 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1670
1671 err = 0;
1672 do_intr = 0;
1673
1674 xfer = devep->ep_xfer;
1675 USB_DATA_XFER_LOCK(xfer);
1676
1677 /* outstanding requests queued up */
1678 if (dev->dev_ue->ue_data != NULL) {
1679 err = dev->dev_ue->ue_data(dev->dev_sc, xfer,
1680 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2);
1681 if (err == USB_ERR_CANCELLED) {
1682 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) ==
1683 USB_NAK)
1684 err = XHCI_TRB_ERROR_SUCCESS;
1685 } else {
1686 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1687 &do_intr);
1688 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) {
1689 pci_xhci_assert_interrupt(sc);
1690 }
1691
1692
1693 /* XXX should not do it if error? */
1694 USB_DATA_XFER_RESET(xfer);
1695 }
1696 }
1697
1698 USB_DATA_XFER_UNLOCK(xfer);
1699
1700
1701 return (err);
1702 }
1703
1704
1705 static int
pci_xhci_handle_transfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,struct xhci_trb * trb,uint32_t slot,uint32_t epid,uint64_t addr,uint32_t ccs,uint32_t streamid)1706 pci_xhci_handle_transfer(struct pci_xhci_softc *sc,
1707 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1708 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot,
1709 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid)
1710 {
1711 struct xhci_trb *setup_trb;
1712 struct usb_data_xfer *xfer;
1713 struct usb_data_xfer_block *xfer_block;
1714 uint64_t val;
1715 uint32_t trbflags;
1716 int do_intr, err;
1717 int do_retry;
1718
1719 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0,
1720 XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1721
1722 xfer = devep->ep_xfer;
1723 USB_DATA_XFER_LOCK(xfer);
1724
1725 DPRINTF(("pci_xhci handle_transfer slot %u", slot));
1726
1727 retry:
1728 err = 0;
1729 do_retry = 0;
1730 do_intr = 0;
1731 setup_trb = NULL;
1732
1733 while (1) {
1734 pci_xhci_dump_trb(trb);
1735
1736 trbflags = trb->dwTrb3;
1737
1738 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK &&
1739 (trbflags & XHCI_TRB_3_CYCLE_BIT) !=
1740 (ccs & XHCI_TRB_3_CYCLE_BIT)) {
1741 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x",
1742 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs));
1743 break;
1744 }
1745
1746 xfer_block = NULL;
1747
1748 switch (XHCI_TRB_3_TYPE_GET(trbflags)) {
1749 case XHCI_TRB_TYPE_LINK:
1750 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1751 ccs ^= 0x1;
1752
1753 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1754 (void *)addr, ccs);
1755 xfer_block->processed = 1;
1756 break;
1757
1758 case XHCI_TRB_TYPE_SETUP_STAGE:
1759 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 ||
1760 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) {
1761 DPRINTF(("pci_xhci: invalid setup trb"));
1762 err = XHCI_TRB_ERROR_TRB;
1763 goto errout;
1764 }
1765 setup_trb = trb;
1766
1767 val = trb->qwTrb0;
1768 if (!xfer->ureq)
1769 xfer->ureq = malloc(
1770 sizeof(struct usb_device_request));
1771 memcpy(xfer->ureq, &val,
1772 sizeof(struct usb_device_request));
1773
1774 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1775 (void *)addr, ccs);
1776 xfer_block->processed = 1;
1777 break;
1778
1779 case XHCI_TRB_TYPE_NORMAL:
1780 case XHCI_TRB_TYPE_ISOCH:
1781 if (setup_trb != NULL) {
1782 DPRINTF(("pci_xhci: trb not supposed to be in "
1783 "ctl scope"));
1784 err = XHCI_TRB_ERROR_TRB;
1785 goto errout;
1786 }
1787 /* fall through */
1788
1789 case XHCI_TRB_TYPE_DATA_STAGE:
1790 xfer_block = usb_data_xfer_append(xfer,
1791 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ?
1792 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)),
1793 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs);
1794 break;
1795
1796 case XHCI_TRB_TYPE_STATUS_STAGE:
1797 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1798 (void *)addr, ccs);
1799 break;
1800
1801 case XHCI_TRB_TYPE_NOOP:
1802 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1803 (void *)addr, ccs);
1804 xfer_block->processed = 1;
1805 break;
1806
1807 case XHCI_TRB_TYPE_EVENT_DATA:
1808 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1809 (void *)addr, ccs);
1810 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) {
1811 xfer_block->processed = 1;
1812 }
1813 break;
1814
1815 default:
1816 DPRINTF(("pci_xhci: handle xfer unexpected trb type "
1817 "0x%x",
1818 XHCI_TRB_3_TYPE_GET(trbflags)));
1819 err = XHCI_TRB_ERROR_TRB;
1820 goto errout;
1821 }
1822
1823 trb = pci_xhci_trb_next(sc, trb, &addr);
1824
1825 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb));
1826
1827 if (xfer_block) {
1828 xfer_block->trbnext = addr;
1829 xfer_block->streamid = streamid;
1830 }
1831
1832 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) &&
1833 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) {
1834 break;
1835 }
1836
1837 /* handle current batch that requires interrupt on complete */
1838 if (trbflags & XHCI_TRB_3_IOC_BIT) {
1839 DPRINTF(("pci_xhci: trb IOC bit set"));
1840 if (epid == 1)
1841 do_retry = 1;
1842 break;
1843 }
1844 }
1845
1846 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata));
1847
1848 if (xfer->ndata <= 0)
1849 goto errout;
1850
1851 if (epid == 1) {
1852 err = USB_ERR_NOT_STARTED;
1853 if (dev->dev_ue->ue_request != NULL)
1854 err = dev->dev_ue->ue_request(dev->dev_sc, xfer);
1855 setup_trb = NULL;
1856 } else {
1857 /* handle data transfer */
1858 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1859 err = XHCI_TRB_ERROR_SUCCESS;
1860 goto errout;
1861 }
1862
1863 err = USB_TO_XHCI_ERR(err);
1864 if ((err == XHCI_TRB_ERROR_SUCCESS) ||
1865 (err == XHCI_TRB_ERROR_STALL) ||
1866 (err == XHCI_TRB_ERROR_SHORT_PKT)) {
1867 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, &do_intr);
1868 if (err != XHCI_TRB_ERROR_SUCCESS)
1869 do_retry = 0;
1870 }
1871
1872 errout:
1873 if (err == XHCI_TRB_ERROR_EV_RING_FULL)
1874 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__));
1875
1876 if (!do_retry)
1877 USB_DATA_XFER_UNLOCK(xfer);
1878
1879 if (do_intr)
1880 pci_xhci_assert_interrupt(sc);
1881
1882 if (do_retry) {
1883 USB_DATA_XFER_RESET(xfer);
1884 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs",
1885 __LINE__));
1886 goto retry;
1887 }
1888
1889 if (epid == 1)
1890 USB_DATA_XFER_RESET(xfer);
1891
1892 return (err);
1893 }
1894
1895 static void
pci_xhci_device_doorbell(struct pci_xhci_softc * sc,uint32_t slot,uint32_t epid,uint32_t streamid)1896 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot,
1897 uint32_t epid, uint32_t streamid)
1898 {
1899 struct pci_xhci_dev_emu *dev;
1900 struct pci_xhci_dev_ep *devep;
1901 struct xhci_dev_ctx *dev_ctx;
1902 struct xhci_endp_ctx *ep_ctx;
1903 struct pci_xhci_trb_ring *sctx_tr;
1904 struct xhci_trb *trb;
1905 uint64_t ringaddr;
1906 uint32_t ccs;
1907
1908 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u",
1909 slot, epid, streamid));
1910
1911 if (slot == 0 || slot > sc->ndevices) {
1912 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot));
1913 return;
1914 }
1915
1916 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) {
1917 DPRINTF(("pci_xhci: invalid endpoint %u", epid));
1918 return;
1919 }
1920
1921 dev = XHCI_SLOTDEV_PTR(sc, slot);
1922 devep = &dev->eps[epid];
1923 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1924 if (!dev_ctx) {
1925 return;
1926 }
1927 ep_ctx = &dev_ctx->ctx_ep[epid];
1928
1929 sctx_tr = NULL;
1930
1931 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x",
1932 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1933 ep_ctx->dwEpCtx4));
1934
1935 if (ep_ctx->qwEpCtx2 == 0)
1936 return;
1937
1938 /* handle pending transfers */
1939 if (devep->ep_xfer->ndata > 0) {
1940 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1941 return;
1942 }
1943
1944 /* get next trb work item */
1945 if (devep->ep_MaxPStreams != 0) {
1946 struct xhci_stream_ctx *sctx;
1947
1948 /*
1949 * Stream IDs of 0, 65535 (any stream), and 65534
1950 * (prime) are invalid.
1951 */
1952 if (streamid == 0 || streamid == 65534 || streamid == 65535) {
1953 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1954 return;
1955 }
1956
1957 sctx = NULL;
1958 pci_xhci_find_stream(sc, ep_ctx, devep, streamid, &sctx);
1959 if (sctx == NULL) {
1960 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1961 return;
1962 }
1963 sctx_tr = &devep->ep_sctx_trbs[streamid];
1964 ringaddr = sctx_tr->ringaddr;
1965 ccs = sctx_tr->ccs;
1966 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL);
1967 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x",
1968 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
1969 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
1970 } else {
1971 if (streamid != 0) {
1972 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1973 return;
1974 }
1975 ringaddr = devep->ep_ringaddr;
1976 ccs = devep->ep_ccs;
1977 trb = devep->ep_tr;
1978 DPRINTF(("doorbell, ccs %lx, trb ccs %x",
1979 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
1980 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
1981 }
1982
1983 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) {
1984 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?",
1985 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid));
1986 return;
1987 }
1988
1989 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid,
1990 ringaddr, ccs, streamid);
1991 }
1992
1993 static void
pci_xhci_dbregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)1994 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset,
1995 uint64_t value)
1996 {
1997
1998 offset = (offset - sc->dboff) / sizeof(uint32_t);
1999
2000 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx",
2001 offset, value));
2002
2003 if (XHCI_HALTED(sc)) {
2004 DPRINTF(("pci_xhci: controller halted"));
2005 return;
2006 }
2007
2008 if (offset == 0)
2009 pci_xhci_complete_commands(sc);
2010 else if (sc->portregs != NULL)
2011 pci_xhci_device_doorbell(sc, offset,
2012 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value));
2013 }
2014
2015 static void
pci_xhci_rtsregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2016 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2017 uint64_t value)
2018 {
2019 struct pci_xhci_rtsregs *rts;
2020
2021 offset -= sc->rtsoff;
2022
2023 if (offset == 0) {
2024 DPRINTF(("pci_xhci attempted write to MFINDEX"));
2025 return;
2026 }
2027
2028 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx",
2029 offset, value));
2030
2031 offset -= 0x20; /* start of intrreg */
2032
2033 rts = &sc->rtsregs;
2034
2035 switch (offset) {
2036 case 0x00:
2037 if (value & XHCI_IMAN_INTR_PEND)
2038 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2039 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) |
2040 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND);
2041
2042 if (!(value & XHCI_IMAN_INTR_ENA))
2043 pci_xhci_deassert_interrupt(sc);
2044
2045 break;
2046
2047 case 0x04:
2048 rts->intrreg.imod = value;
2049 break;
2050
2051 case 0x08:
2052 rts->intrreg.erstsz = value & 0xFFFF;
2053 break;
2054
2055 case 0x10:
2056 /* ERSTBA low bits */
2057 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) |
2058 (value & ~0x3F);
2059 break;
2060
2061 case 0x14:
2062 /* ERSTBA high bits */
2063 rts->intrreg.erstba = (value << 32) |
2064 MASK_64_LO(sc->rtsregs.intrreg.erstba);
2065
2066 rts->erstba_p = XHCI_GADDR(sc,
2067 sc->rtsregs.intrreg.erstba & ~0x3FUL);
2068
2069 rts->erst_p = XHCI_GADDR(sc,
2070 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL);
2071
2072 rts->er_enq_idx = 0;
2073 rts->er_events_cnt = 0;
2074
2075 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u",
2076 rts->erstba_p,
2077 rts->erstba_p->qwEvrsTablePtr,
2078 rts->erstba_p->dwEvrsTableSize));
2079 break;
2080
2081 case 0x18:
2082 /* ERDP low bits */
2083 rts->intrreg.erdp =
2084 MASK_64_HI(sc->rtsregs.intrreg.erdp) |
2085 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) |
2086 (value & ~0xF);
2087 if (value & XHCI_ERDP_LO_BUSY) {
2088 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY;
2089 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2090 }
2091
2092 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value);
2093
2094 break;
2095
2096 case 0x1C:
2097 /* ERDP high bits */
2098 rts->intrreg.erdp = (value << 32) |
2099 MASK_64_LO(sc->rtsregs.intrreg.erdp);
2100
2101 if (rts->er_events_cnt > 0) {
2102 uint64_t erdp;
2103 uint32_t erdp_i;
2104
2105 erdp = rts->intrreg.erdp & ~0xF;
2106 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) /
2107 sizeof(struct xhci_trb);
2108
2109 if (erdp_i <= rts->er_enq_idx)
2110 rts->er_events_cnt = rts->er_enq_idx - erdp_i;
2111 else
2112 rts->er_events_cnt =
2113 rts->erstba_p->dwEvrsTableSize -
2114 (erdp_i - rts->er_enq_idx);
2115
2116 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u",
2117 erdp, rts->er_events_cnt));
2118 }
2119
2120 break;
2121
2122 default:
2123 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx",
2124 offset));
2125 break;
2126 }
2127 }
2128
2129 static uint64_t
pci_xhci_portregs_read(struct pci_xhci_softc * sc,uint64_t offset)2130 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2131 {
2132 int port;
2133 uint32_t *p;
2134
2135 if (sc->portregs == NULL)
2136 return (0);
2137
2138 port = (offset - 0x3F0) / 0x10;
2139
2140 if (port > XHCI_MAX_DEVS) {
2141 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS",
2142 port));
2143
2144 /* return default value for unused port */
2145 return (XHCI_PS_SPEED_SET(3));
2146 }
2147
2148 offset = (offset - 0x3F0) % 0x10;
2149
2150 p = &sc->portregs[port].portsc;
2151 p += offset / sizeof(uint32_t);
2152
2153 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x",
2154 offset, port, *p));
2155
2156 return (*p);
2157 }
2158
2159 static void
pci_xhci_hostop_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2160 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset,
2161 uint64_t value)
2162 {
2163 offset -= XHCI_CAPLEN;
2164
2165 if (offset < 0x400)
2166 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx",
2167 offset, value));
2168
2169 switch (offset) {
2170 case XHCI_USBCMD:
2171 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F);
2172 break;
2173
2174 case XHCI_USBSTS:
2175 /* clear bits on write */
2176 sc->opregs.usbsts &= ~(value &
2177 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS|
2178 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR));
2179 break;
2180
2181 case XHCI_PAGESIZE:
2182 /* read only */
2183 break;
2184
2185 case XHCI_DNCTRL:
2186 sc->opregs.dnctrl = value & 0xFFFF;
2187 break;
2188
2189 case XHCI_CRCR_LO:
2190 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) {
2191 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2192 sc->opregs.crcr |= value &
2193 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2194 } else {
2195 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) |
2196 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS));
2197 }
2198 break;
2199
2200 case XHCI_CRCR_HI:
2201 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) {
2202 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) |
2203 (value << 32);
2204
2205 sc->opregs.cr_p = XHCI_GADDR(sc,
2206 sc->opregs.crcr & ~0xF);
2207 }
2208
2209 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) {
2210 /* Stop operation of Command Ring */
2211 }
2212
2213 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) {
2214 /* Abort command */
2215 }
2216
2217 break;
2218
2219 case XHCI_DCBAAP_LO:
2220 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) |
2221 (value & 0xFFFFFFC0);
2222 break;
2223
2224 case XHCI_DCBAAP_HI:
2225 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) |
2226 (value << 32);
2227 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL);
2228
2229 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)",
2230 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p));
2231 break;
2232
2233 case XHCI_CONFIG:
2234 sc->opregs.config = value & 0x03FF;
2235 break;
2236
2237 default:
2238 if (offset >= 0x400)
2239 pci_xhci_portregs_write(sc, offset, value);
2240
2241 break;
2242 }
2243 }
2244
2245
2246 static void
pci_xhci_write(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)2247 pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2248 int baridx, uint64_t offset, int size, uint64_t value)
2249 {
2250 struct pci_xhci_softc *sc;
2251
2252 sc = pi->pi_arg;
2253
2254 assert(baridx == 0);
2255
2256
2257 pthread_mutex_lock(&sc->mtx);
2258 if (offset < XHCI_CAPLEN) /* read only registers */
2259 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset));
2260 else if (offset < sc->dboff)
2261 pci_xhci_hostop_write(sc, offset, value);
2262 else if (offset < sc->rtsoff)
2263 pci_xhci_dbregs_write(sc, offset, value);
2264 else if (offset < sc->regsend)
2265 pci_xhci_rtsregs_write(sc, offset, value);
2266 else
2267 WPRINTF(("pci_xhci: write invalid offset %ld", offset));
2268
2269 pthread_mutex_unlock(&sc->mtx);
2270 }
2271
2272 static uint64_t
pci_xhci_hostcap_read(struct pci_xhci_softc * sc,uint64_t offset)2273 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset)
2274 {
2275 uint64_t value;
2276
2277 switch (offset) {
2278 case XHCI_CAPLENGTH: /* 0x00 */
2279 value = sc->caplength;
2280 break;
2281
2282 case XHCI_HCSPARAMS1: /* 0x04 */
2283 value = sc->hcsparams1;
2284 break;
2285
2286 case XHCI_HCSPARAMS2: /* 0x08 */
2287 value = sc->hcsparams2;
2288 break;
2289
2290 case XHCI_HCSPARAMS3: /* 0x0C */
2291 value = sc->hcsparams3;
2292 break;
2293
2294 case XHCI_HCSPARAMS0: /* 0x10 */
2295 value = sc->hccparams1;
2296 break;
2297
2298 case XHCI_DBOFF: /* 0x14 */
2299 value = sc->dboff;
2300 break;
2301
2302 case XHCI_RTSOFF: /* 0x18 */
2303 value = sc->rtsoff;
2304 break;
2305
2306 case XHCI_HCCPRAMS2: /* 0x1C */
2307 value = sc->hccparams2;
2308 break;
2309
2310 default:
2311 value = 0;
2312 break;
2313 }
2314
2315 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx",
2316 offset, value));
2317
2318 return (value);
2319 }
2320
2321 static uint64_t
pci_xhci_hostop_read(struct pci_xhci_softc * sc,uint64_t offset)2322 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset)
2323 {
2324 uint64_t value;
2325
2326 offset = (offset - XHCI_CAPLEN);
2327
2328 switch (offset) {
2329 case XHCI_USBCMD: /* 0x00 */
2330 value = sc->opregs.usbcmd;
2331 break;
2332
2333 case XHCI_USBSTS: /* 0x04 */
2334 value = sc->opregs.usbsts;
2335 break;
2336
2337 case XHCI_PAGESIZE: /* 0x08 */
2338 value = sc->opregs.pgsz;
2339 break;
2340
2341 case XHCI_DNCTRL: /* 0x14 */
2342 value = sc->opregs.dnctrl;
2343 break;
2344
2345 case XHCI_CRCR_LO: /* 0x18 */
2346 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR;
2347 break;
2348
2349 case XHCI_CRCR_HI: /* 0x1C */
2350 value = 0;
2351 break;
2352
2353 case XHCI_DCBAAP_LO: /* 0x30 */
2354 value = sc->opregs.dcbaap & 0xFFFFFFFF;
2355 break;
2356
2357 case XHCI_DCBAAP_HI: /* 0x34 */
2358 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF;
2359 break;
2360
2361 case XHCI_CONFIG: /* 0x38 */
2362 value = sc->opregs.config;
2363 break;
2364
2365 default:
2366 if (offset >= 0x400)
2367 value = pci_xhci_portregs_read(sc, offset);
2368 else
2369 value = 0;
2370
2371 break;
2372 }
2373
2374 if (offset < 0x400)
2375 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx",
2376 offset, value));
2377
2378 return (value);
2379 }
2380
2381 static uint64_t
pci_xhci_dbregs_read(struct pci_xhci_softc * sc,uint64_t offset)2382 pci_xhci_dbregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2383 {
2384
2385 /* read doorbell always returns 0 */
2386 return (0);
2387 }
2388
2389 static uint64_t
pci_xhci_rtsregs_read(struct pci_xhci_softc * sc,uint64_t offset)2390 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2391 {
2392 uint32_t value;
2393
2394 offset -= sc->rtsoff;
2395 value = 0;
2396
2397 if (offset == XHCI_MFINDEX) {
2398 value = sc->rtsregs.mfindex;
2399 } else if (offset >= 0x20) {
2400 int item;
2401 uint32_t *p;
2402
2403 offset -= 0x20;
2404 item = offset % 32;
2405
2406 assert(offset < sizeof(sc->rtsregs.intrreg));
2407
2408 p = &sc->rtsregs.intrreg.iman;
2409 p += item / sizeof(uint32_t);
2410 value = *p;
2411 }
2412
2413 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x",
2414 offset, value));
2415
2416 return (value);
2417 }
2418
2419 static uint64_t
pci_xhci_xecp_read(struct pci_xhci_softc * sc,uint64_t offset)2420 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset)
2421 {
2422 uint32_t value;
2423
2424 offset -= sc->regsend;
2425 value = 0;
2426
2427 switch (offset) {
2428 case 0:
2429 /* rev major | rev minor | next-cap | cap-id */
2430 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS;
2431 break;
2432 case 4:
2433 /* name string = "USB" */
2434 value = 0x20425355;
2435 break;
2436 case 8:
2437 /* psic | proto-defined | compat # | compat offset */
2438 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start;
2439 break;
2440 case 12:
2441 break;
2442 case 16:
2443 /* rev major | rev minor | next-cap | cap-id */
2444 value = (0x03 << 24) | XHCI_ID_PROTOCOLS;
2445 break;
2446 case 20:
2447 /* name string = "USB" */
2448 value = 0x20425355;
2449 break;
2450 case 24:
2451 /* psic | proto-defined | compat # | compat offset */
2452 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start;
2453 break;
2454 case 28:
2455 break;
2456 default:
2457 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset));
2458 break;
2459 }
2460
2461 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x",
2462 offset, value));
2463
2464 return (value);
2465 }
2466
2467
2468 static uint64_t
pci_xhci_read(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size)2469 pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2470 uint64_t offset, int size)
2471 {
2472 struct pci_xhci_softc *sc;
2473 uint32_t value;
2474
2475 sc = pi->pi_arg;
2476
2477 assert(baridx == 0);
2478
2479 pthread_mutex_lock(&sc->mtx);
2480 if (offset < XHCI_CAPLEN)
2481 value = pci_xhci_hostcap_read(sc, offset);
2482 else if (offset < sc->dboff)
2483 value = pci_xhci_hostop_read(sc, offset);
2484 else if (offset < sc->rtsoff)
2485 value = pci_xhci_dbregs_read(sc, offset);
2486 else if (offset < sc->regsend)
2487 value = pci_xhci_rtsregs_read(sc, offset);
2488 else if (offset < (sc->regsend + 4*32))
2489 value = pci_xhci_xecp_read(sc, offset);
2490 else {
2491 value = 0;
2492 WPRINTF(("pci_xhci: read invalid offset %ld", offset));
2493 }
2494
2495 pthread_mutex_unlock(&sc->mtx);
2496
2497 switch (size) {
2498 case 1:
2499 value &= 0xFF;
2500 break;
2501 case 2:
2502 value &= 0xFFFF;
2503 break;
2504 case 4:
2505 value &= 0xFFFFFFFF;
2506 break;
2507 }
2508
2509 return (value);
2510 }
2511
2512 static void
pci_xhci_reset_port(struct pci_xhci_softc * sc,int portn,int warm)2513 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm)
2514 {
2515 struct pci_xhci_portregs *port;
2516 struct pci_xhci_dev_emu *dev;
2517 struct xhci_trb evtrb;
2518 int error;
2519
2520 assert(portn <= XHCI_MAX_DEVS);
2521
2522 DPRINTF(("xhci reset port %d", portn));
2523
2524 port = XHCI_PORTREG_PTR(sc, portn);
2525 dev = XHCI_DEVINST_PTR(sc, portn);
2526 if (dev) {
2527 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC);
2528 port->portsc |= XHCI_PS_PED |
2529 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2530
2531 if (warm && dev->dev_ue->ue_usbver == 3) {
2532 port->portsc |= XHCI_PS_WRC;
2533 }
2534
2535 if ((port->portsc & XHCI_PS_PRC) == 0) {
2536 port->portsc |= XHCI_PS_PRC;
2537
2538 pci_xhci_set_evtrb(&evtrb, portn,
2539 XHCI_TRB_ERROR_SUCCESS,
2540 XHCI_TRB_EVENT_PORT_STS_CHANGE);
2541 error = pci_xhci_insert_event(sc, &evtrb, 1);
2542 if (error != XHCI_TRB_ERROR_SUCCESS)
2543 DPRINTF(("xhci reset port insert event "
2544 "failed"));
2545 }
2546 }
2547 }
2548
2549 static void
pci_xhci_init_port(struct pci_xhci_softc * sc,int portn)2550 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
2551 {
2552 struct pci_xhci_portregs *port;
2553 struct pci_xhci_dev_emu *dev;
2554
2555 port = XHCI_PORTREG_PTR(sc, portn);
2556 dev = XHCI_DEVINST_PTR(sc, portn);
2557 if (dev) {
2558 port->portsc = XHCI_PS_CCS | /* connected */
2559 XHCI_PS_PP; /* port power */
2560
2561 if (dev->dev_ue->ue_usbver == 2) {
2562 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
2563 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2564 } else {
2565 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) |
2566 XHCI_PS_PED | /* enabled */
2567 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2568 }
2569
2570 DPRINTF(("Init port %d 0x%x", portn, port->portsc));
2571 } else {
2572 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;
2573 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc));
2574 }
2575 }
2576
2577 static int
pci_xhci_dev_intr(struct usb_hci * hci,int epctx)2578 pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
2579 {
2580 struct pci_xhci_dev_emu *dev;
2581 struct xhci_dev_ctx *dev_ctx;
2582 struct xhci_trb evtrb;
2583 struct pci_xhci_softc *sc;
2584 struct pci_xhci_portregs *p;
2585 struct xhci_endp_ctx *ep_ctx;
2586 int error = 0;
2587 int dir_in;
2588 int epid;
2589
2590 dir_in = epctx & 0x80;
2591 epid = epctx & ~0x80;
2592
2593 /* HW endpoint contexts are 0-15; convert to epid based on dir */
2594 epid = (epid * 2) + (dir_in ? 1 : 0);
2595
2596 assert(epid >= 1 && epid <= 31);
2597
2598 dev = hci->hci_sc;
2599 sc = dev->xsc;
2600
2601 /* check if device is ready; OS has to initialise it */
2602 if (sc->rtsregs.erstba_p == NULL ||
2603 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 ||
2604 dev->dev_ctx == NULL)
2605 return (0);
2606
2607 p = XHCI_PORTREG_PTR(sc, hci->hci_port);
2608
2609 /* raise event if link U3 (suspended) state */
2610 if (XHCI_PS_PLS_GET(p->portsc) == 3) {
2611 p->portsc &= ~XHCI_PS_PLS_MASK;
2612 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME);
2613 if ((p->portsc & XHCI_PS_PLC) != 0)
2614 return (0);
2615
2616 p->portsc |= XHCI_PS_PLC;
2617
2618 pci_xhci_set_evtrb(&evtrb, hci->hci_port,
2619 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE);
2620 error = pci_xhci_insert_event(sc, &evtrb, 0);
2621 if (error != XHCI_TRB_ERROR_SUCCESS)
2622 goto done;
2623 }
2624
2625 dev_ctx = dev->dev_ctx;
2626 ep_ctx = &dev_ctx->ctx_ep[epid];
2627 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) {
2628 DPRINTF(("xhci device interrupt on disabled endpoint %d",
2629 epid));
2630 return (0);
2631 }
2632
2633 DPRINTF(("xhci device interrupt on endpoint %d", epid));
2634
2635 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0);
2636
2637 done:
2638 return (error);
2639 }
2640
2641 static int
pci_xhci_dev_event(struct usb_hci * hci,enum hci_usbev evid,void * param)2642 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid, void *param)
2643 {
2644
2645 DPRINTF(("xhci device event port %d", hci->hci_port));
2646 return (0);
2647 }
2648
2649
2650
2651 static void
pci_xhci_device_usage(char * opt)2652 pci_xhci_device_usage(char *opt)
2653 {
2654
2655 EPRINTLN("Invalid USB emulation \"%s\"", opt);
2656 }
2657
2658 static int
pci_xhci_parse_opts(struct pci_xhci_softc * sc,char * opts)2659 pci_xhci_parse_opts(struct pci_xhci_softc *sc, char *opts)
2660 {
2661 struct pci_xhci_dev_emu **devices;
2662 struct pci_xhci_dev_emu *dev;
2663 struct usb_devemu *ue;
2664 void *devsc;
2665 char *uopt, *xopts, *config;
2666 int usb3_port, usb2_port, i;
2667
2668 uopt = NULL;
2669 usb3_port = sc->usb3_port_start - 1;
2670 usb2_port = sc->usb2_port_start - 1;
2671 devices = NULL;
2672
2673 if (opts == NULL)
2674 goto portsfinal;
2675
2676 devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *));
2677
2678 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *));
2679 sc->devices = devices;
2680 sc->ndevices = 0;
2681
2682 uopt = strdup(opts);
2683 for (xopts = strtok(uopt, ",");
2684 xopts != NULL;
2685 xopts = strtok(NULL, ",")) {
2686 if (usb2_port == ((sc->usb2_port_start-1) + XHCI_MAX_DEVS/2) ||
2687 usb3_port == ((sc->usb3_port_start-1) + XHCI_MAX_DEVS/2)) {
2688 WPRINTF(("pci_xhci max number of USB 2 or 3 "
2689 "devices reached, max %d", XHCI_MAX_DEVS/2));
2690 usb2_port = usb3_port = -1;
2691 goto done;
2692 }
2693
2694 /* device[=<config>] */
2695 if ((config = strchr(xopts, '=')) == NULL)
2696 config = ""; /* no config */
2697 else
2698 *config++ = '\0';
2699
2700 ue = usb_emu_finddev(xopts);
2701 if (ue == NULL) {
2702 pci_xhci_device_usage(xopts);
2703 DPRINTF(("pci_xhci device not found %s", xopts));
2704 usb2_port = usb3_port = -1;
2705 goto done;
2706 }
2707
2708 DPRINTF(("pci_xhci adding device %s, opts \"%s\"",
2709 xopts, config));
2710
2711 dev = calloc(1, sizeof(struct pci_xhci_dev_emu));
2712 dev->xsc = sc;
2713 dev->hci.hci_sc = dev;
2714 dev->hci.hci_intr = pci_xhci_dev_intr;
2715 dev->hci.hci_event = pci_xhci_dev_event;
2716
2717 if (ue->ue_usbver == 2) {
2718 dev->hci.hci_port = usb2_port + 1;
2719 devices[usb2_port] = dev;
2720 usb2_port++;
2721 } else {
2722 dev->hci.hci_port = usb3_port + 1;
2723 devices[usb3_port] = dev;
2724 usb3_port++;
2725 }
2726
2727 dev->hci.hci_address = 0;
2728 devsc = ue->ue_init(&dev->hci, config);
2729 if (devsc == NULL) {
2730 pci_xhci_device_usage(xopts);
2731 usb2_port = usb3_port = -1;
2732 goto done;
2733 }
2734
2735 dev->dev_ue = ue;
2736 dev->dev_sc = devsc;
2737
2738 /* assign slot number to device */
2739 sc->slots[sc->ndevices] = dev;
2740
2741 sc->ndevices++;
2742 }
2743
2744 portsfinal:
2745 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs));
2746
2747 if (sc->ndevices > 0) {
2748 /* port and slot numbering start from 1 */
2749 sc->devices--;
2750 sc->portregs--;
2751 sc->slots--;
2752
2753 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2754 pci_xhci_init_port(sc, i);
2755 }
2756 } else {
2757 WPRINTF(("pci_xhci no USB devices configured"));
2758 sc->ndevices = 1;
2759 }
2760
2761 done:
2762 if (devices != NULL) {
2763 if (usb2_port <= 0 && usb3_port <= 0) {
2764 sc->devices = NULL;
2765 for (i = 0; devices[i] != NULL; i++)
2766 free(devices[i]);
2767 sc->ndevices = -1;
2768
2769 free(devices);
2770 }
2771 }
2772 free(uopt);
2773 return (sc->ndevices);
2774 }
2775
2776 static int
pci_xhci_init(struct vmctx * ctx,struct pci_devinst * pi,char * opts)2777 pci_xhci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2778 {
2779 struct pci_xhci_softc *sc;
2780 int error;
2781
2782 if (xhci_in_use) {
2783 WPRINTF(("pci_xhci controller already defined"));
2784 return (-1);
2785 }
2786 xhci_in_use = 1;
2787
2788 sc = calloc(1, sizeof(struct pci_xhci_softc));
2789 pi->pi_arg = sc;
2790 sc->xsc_pi = pi;
2791
2792 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1;
2793 sc->usb3_port_start = 1;
2794
2795 /* discover devices */
2796 error = pci_xhci_parse_opts(sc, opts);
2797 if (error < 0)
2798 goto done;
2799 else
2800 error = 0;
2801
2802 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) |
2803 XHCI_SET_HCIVERSION(0x0100);
2804 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) |
2805 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */
2806 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS);
2807 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) |
2808 XHCI_SET_HCSP2_IST(0x04);
2809 sc->hcsparams3 = 0; /* no latency */
2810 sc->hccparams1 = XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */
2811 XHCI_SET_HCCP1_SPC(1) | /* short packet */
2812 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX);
2813 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) |
2814 XHCI_SET_HCCP2_U3C(1);
2815 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START +
2816 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs));
2817
2818 /* dboff must be 32-bit aligned */
2819 if (sc->dboff & 0x3)
2820 sc->dboff = (sc->dboff + 0x3) & ~0x3;
2821
2822 /* rtsoff must be 32-bytes aligned */
2823 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32);
2824 if (sc->rtsoff & 0x1F)
2825 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F;
2826
2827 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff,
2828 sc->rtsoff));
2829
2830 sc->opregs.usbsts = XHCI_STS_HCH;
2831 sc->opregs.pgsz = XHCI_PAGESIZE_4K;
2832
2833 pci_xhci_reset(sc);
2834
2835 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */
2836
2837 /*
2838 * Set extended capabilities pointer to be after regsend;
2839 * value of xecp field is 32-bit offset.
2840 */
2841 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4);
2842
2843 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31);
2844 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2845 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS);
2846 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB);
2847 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI);
2848 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0);
2849
2850 pci_emul_add_msicap(pi, 1);
2851
2852 /* regsend + xecp registers */
2853 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32);
2854 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32));
2855
2856
2857 pci_lintr_request(pi);
2858
2859 pthread_mutex_init(&sc->mtx, NULL);
2860
2861 done:
2862 if (error) {
2863 free(sc);
2864 }
2865
2866 return (error);
2867 }
2868
2869
2870
2871 struct pci_devemu pci_de_xhci = {
2872 .pe_emu = "xhci",
2873 .pe_init = pci_xhci_init,
2874 .pe_barwrite = pci_xhci_write,
2875 .pe_barread = pci_xhci_read
2876 };
2877 PCI_EMUL_SET(pci_de_xhci);
2878