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Searched refs:WriteRes (Results 1 – 25 of 48) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVSchedRocket.td47 def : WriteRes<WriteJmp, [RocketUnitB]>;
48 def : WriteRes<WriteJal, [RocketUnitB]>;
49 def : WriteRes<WriteJalr, [RocketUnitB]>;
50 def : WriteRes<WriteJmpReg, [RocketUnitB]>;
53 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
54 def : WriteRes<WriteIALU, [RocketUnitALU]>;
55 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
56 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
57 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
58 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
[all …]
DRISCVSchedSiFive7.td39 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
40 def : WriteRes<WriteJal, [SiFive7PipeB]>;
41 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
42 def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
46 def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
47 def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
48 def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>;
49 def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>;
50 def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>;
51 def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>;
[all …]
DRISCVScheduleV.td483 def : WriteRes<WriteVLDE8, []>;
484 def : WriteRes<WriteVLDE16, []>;
485 def : WriteRes<WriteVLDE32, []>;
486 def : WriteRes<WriteVLDE64, []>;
487 def : WriteRes<WriteVSTE8, []>;
488 def : WriteRes<WriteVSTE16, []>;
489 def : WriteRes<WriteVSTE32, []>;
490 def : WriteRes<WriteVSTE64, []>;
491 def : WriteRes<WriteVLDM, []>;
492 def : WriteRes<WriteVSTM, []>;
[all …]
DRISCVScheduleB.td53 def : WriteRes<WriteSHXADD, []>;
54 def : WriteRes<WriteSHXADD32, []>;
63 def : WriteRes<WriteRotateImm, []>;
64 def : WriteRes<WriteRotateImm32, []>;
65 def : WriteRes<WriteRotateReg, []>;
66 def : WriteRes<WriteRotateReg32, []>;
67 def : WriteRes<WriteCLZ, []>;
68 def : WriteRes<WriteCLZ32, []>;
69 def : WriteRes<WriteCTZ, []>;
70 def : WriteRes<WriteCTZ32, []>;
[all …]
DRISCVSchedule.td187 def : WriteRes<WriteFALU16, []>;
188 def : WriteRes<WriteFClass16, []>;
189 def : WriteRes<WriteFCvtF16ToF64, []>;
190 def : WriteRes<WriteFCvtF64ToF16, []>;
191 def : WriteRes<WriteFCvtI64ToF16, []>;
192 def : WriteRes<WriteFCvtF32ToF16, []>;
193 def : WriteRes<WriteFCvtI32ToF16, []>;
194 def : WriteRes<WriteFCvtF16ToI64, []>;
195 def : WriteRes<WriteFCvtF16ToF32, []>;
196 def : WriteRes<WriteFCvtF16ToI32, []>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td69 // These WriteRes entries are not used in the Falkor sched model.
70 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
71 def : WriteRes<WriteI, []> { let Unsupported = 1; }
72 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
73 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
75 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
76 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
78 def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
[all …]
DAArch64SchedKryo.td65 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
66 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
69 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
71 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
73 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
74 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
76 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
78 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
79 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
[all …]
DAArch64SchedThunderX.td51 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
52 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
53 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
54 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
56 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
59 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
64 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
70 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
75 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
[all …]
DAArch64SchedA53.td60 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
65 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
68 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
69 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
72 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
73 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
[all …]
DAArch64SchedA55.td63 def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ
64 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
65 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
66 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
67 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
68 def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; } // Shift/Scale
71 def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; } // 32-bit Multiply
72 def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit Multiply
75 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
78 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
[all …]
DAArch64SchedTSV110.td54 def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
55 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
56 def : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; }
57 def : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; }
58 def : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; }
59 def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
62 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
64 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
66 def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
67 def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
[all …]
DAArch64SchedCyclone.td133 def : WriteRes<WriteImm, [CyUnitI]>;
152 def : WriteRes<WriteI, [CyUnitI]>;
158 def : WriteRes<WriteISReg, [CyUnitIS]> {
166 def : WriteRes<WriteIEReg, [CyUnitIS]> {
173 def : WriteRes<WriteIS, [CyUnitIS]>;
178 def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> {
194 def : WriteRes<WriteIM32, [CyUnitIM]> {
198 def : WriteRes<WriteIM64, [CyUnitIM]> {
209 def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
216 def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
[all …]
DAArch64SchedExynosM3.td207 def : WriteRes<WriteID32, [M3UnitC,
210 def : WriteRes<WriteID64, [M3UnitC,
213 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
214 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
226 def : WriteRes<WriteLDHi, []> { let Latency = 4;
237 def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; }
238 def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; }
239 def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12;
241 def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; }
244 def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; }
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
84 def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
86 def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
87 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
88 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
95 def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
96 def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
[all …]
DX86ScheduleAtom.td61 def : WriteRes<SchedRW, RRPorts> {
67 def : WriteRes<SchedRW.Folded, RMPorts> {
74 def : WriteRes<WriteRMW, [AtomPort0]>;
115 def : WriteRes<WriteSETCC, [AtomPort01]>;
116 def : WriteRes<WriteSETCCStore, [AtomPort01]> {
120 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
132 def : WriteRes<WriteLEA, [AtomPort1]>;
164 def : WriteRes<WriteLoad, [AtomPort0]>;
165 def : WriteRes<WriteStore, [AtomPort0]>;
166 def : WriteRes<WriteStoreNT, [AtomPort0]>;
[all …]
DX86SchedSandyBridge.td91 def : WriteRes<SchedRW, ExePorts> {
99 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
108 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
110 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
111 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
113 def : WriteRes<WriteMove, [SBPort015]>;
114 def : WriteRes<WriteZero, []>;
115 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 5; let NumMicroOps = 0; }
132 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
[all …]
DX86SchedSkylakeClient.td95 def : WriteRes<SchedRW, ExePorts> {
103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
158 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
162 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
163 def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
212 def : WriteRes<WriteZero, []>;
418 def : WriteRes<WriteVecInsert, [SKLPort5]> {
423 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
[all …]
DX86SchedHaswell.td101 def : WriteRes<SchedRW, ExePorts> {
109 def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
118 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
126 def : WriteRes<WriteZero, []>;
148 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
173 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
174 def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
190 def : WriteRes<WriteLEA, [HWPort15]>;
470 def : WriteRes<WriteVecInsert, [HWPort5]> {
475 def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
[all …]
DX86ScheduleBtVer2.td126 def : WriteRes<SchedRW, ExePorts> {
134 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
146 def : WriteRes<SchedRW, ExePorts> {
154 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
166 def : WriteRes<SchedRW, ExePorts> {
174 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
227 def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
228 def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
229 def : WriteRes<WriteLAHFSAHF, [JALU01]>;
239 def : WriteRes<WriteLEA, [JALU01]>;
[all …]
DX86SchedBroadwell.td96 def : WriteRes<SchedRW, ExePorts> {
104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
160 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
165 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
166 def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
215 def : WriteRes<WriteZero, []>;
428 def : WriteRes<WriteVecInsert, [BWPort5]> {
433 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
[all …]
DX86ScheduleZnver2.td136 def : WriteRes<SchedRW, ExePorts> {
144 def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
157 def : WriteRes<SchedRW, ExePorts> {
165 def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
174 def : WriteRes<WriteRMW, [Zn2AGU]>;
176 def : WriteRes<WriteStore, [Zn2AGU]>;
177 def : WriteRes<WriteStoreNT, [Zn2AGU]>;
178 def : WriteRes<WriteMove, [Zn2ALU]>;
179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 8; }
183 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 8; let NumMicroOps = 0; }
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMScheduleM7.td56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
60 def : WriteRes<WriteALUsi, [M7UnitALU, M7UnitShift1]>;
61 def : WriteRes<WriteALUsr, [M7UnitALU, M7UnitShift1]>;
62 def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
66 def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
74 def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
[all …]
DARMScheduleR52.td61 def : WriteRes<WriteALU, [R52UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteALUsi, [R52UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteALUsr, [R52UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteALUSsr, [R52UnitALU]> { let Latency = 3; }
67 def : WriteRes<WriteCMP, [R52UnitALU]> { let Latency = 0; }
68 def : WriteRes<WriteCMPsi, [R52UnitALU]> { let Latency = 0; }
69 def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }
74 def : WriteRes<WriteDIV, [R52UnitDiv]> {
79 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
80 def : WriteRes<WriteBrL, [R52UnitB]> { let Latency = 0; }
[all …]
DARMScheduleM4.td37 class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
38 class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
39 class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
40 class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiSchedule.td64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }

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