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Searched refs:WREG32_PLL_P (Results 1 – 4 of 4) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/radeon/
Dradeon_legacy_crtc.c234 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_pll_write_update()
261 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, in radeon_pll2_write_update()
840 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, in radeon_set_pll()
844 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
852 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, in radeon_set_pll()
856 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
860 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
869 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
888 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, in radeon_set_pll()
921 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()
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Dradeon_legacy_tv.c773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
775 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
779 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
784 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); in radeon_legacy_tv_mode_set()
785 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
787 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); in radeon_legacy_tv_mode_set()
788 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); in radeon_legacy_tv_mode_set()
Dradeon_legacy_encoders.c112 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); in radeon_legacy_lvds_update()
Dradeon.h1711 #define WREG32_PLL_P(reg, val, mask) \ macro