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Searched refs:VT (Results 1 – 25 of 282) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp202 template<MVT::SimpleValueType VT>
204 return SelectSVEAddSubImm(N, VT, Imm, Shift); in SelectSVEAddSubImm()
207 template <MVT::SimpleValueType VT, bool Invert = false>
209 return SelectSVELogicalImm(N, VT, Imm, Invert); in SelectSVELogicalImm()
212 template <MVT::SimpleValueType VT>
214 return SelectSVEArithImm(N, VT, Imm); in SelectSVEArithImm()
361 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
363 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm, bool Invert);
369 bool SelectSVEArithImm(SDValue N, MVT VT, SDValue &Imm);
1284 EVT VT = N->getValueType(0); in SelectTable() local
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DAArch64ISelLowering.cpp130 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT() argument
131 switch (VT.getSimpleVT().SimpleTy) { in getPackedSVEVectorVT()
170 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate() argument
171 assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) && in getPromotedVTForPredicate()
173 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
192 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
193 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
195 return VT.isFixedLengthVector() || in isPackedVectorType()
196 VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock; in isPackedVectorType()
315 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
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DAArch64FastISel.cpp182 bool isTypeLegal(Type *Ty, MVT &VT);
183 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
187 bool simplifyAddress(Address &Addr, MVT VT);
225 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
227 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
229 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
236 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
265 unsigned materializeInt(const ConstantInt *CI, MVT VT);
266 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
318 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp216 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
223 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
224 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
225 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
226 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
227 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
495 MVT VT) { in getOUTLINE_ATOMIC() argument
497 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
571 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
574 switch (VT.SimpleTy) { \ in getSYNC()
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DCallingConvLower.cpp95 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
108 MVT VT = Outs[i].VT; in CheckReturn() local
110 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
122 MVT VT = Outs[i].VT; in AnalyzeReturn() local
124 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
135 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
170 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
172 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
175 << EVT(VT).getEVTString() << '\n'; in AnalyzeCallResult()
183 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult() argument
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.h45 bool operator==(EVT VT) const {
46 return !(*this != VT);
48 bool operator!=(EVT VT) const {
49 if (V.SimpleTy != VT.V.SimpleTy)
52 return LLVMTy != VT.LLVMTy;
74 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
76 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
79 return getExtendedVectorVT(Context, VT, NumElements, IsScalable);
84 static EVT getVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getVectorVT()
85 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
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DTargetLowering.h437 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction() argument
439 if (VT.getVectorElementCount().isScalar()) in getPreferredVectorAction()
442 if (!VT.isPow2VectorType()) in getPreferredVectorAction()
473 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap() argument
476 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem() argument
497 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
503 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
509 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
515 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
615 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost() argument
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DSelectionDAG.h103 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
104 FastID(ID), VTs(VT), NumVTs(Num) {
602 SDVTList getVTList(EVT VT);
617 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
619 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
622 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
624 return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL,
625 VT, IsTarget, IsOpaque);
628 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
632 SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp249 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
250 if (EVT(VT).isSimple() && VT != MVT::Other && in DAGCombiner()
251 TLI.isTypeLegal(EVT(VT)) && in DAGCombiner()
252 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits) in DAGCombiner()
253 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize(); in DAGCombiner()
556 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
566 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
766 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation() argument
767 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); in hasOperation()
785 bool isTypeLegal(const EVT &VT) { in isTypeLegal() argument
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DTargetLowering.cpp198 EVT VT = getOptimalMemOpType(Op, FuncAttributes); in findOptimalMemOpLowering() local
200 if (VT == MVT::Other) { in findOptimalMemOpLowering()
204 VT = MVT::i64; in findOptimalMemOpLowering()
206 while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && in findOptimalMemOpLowering()
207 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) in findOptimalMemOpLowering()
208 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
209 assert(VT.isInteger()); in findOptimalMemOpLowering()
219 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
220 VT = LVT; in findOptimalMemOpLowering()
226 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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DSelectionDAG.cpp124 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
126 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
131 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
932 EVT VT = N->getValueType(0); in VerifySDNode() local
934 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
939 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
941 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
1008 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1009 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
1010 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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DLegalizeVectorOps.cpp604 MVT VT = Node->getSimpleValueType(0); in Promote() local
605 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in Promote()
626 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
627 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
629 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
631 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
641 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
642 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in PromoteINT_TO_FP()
643 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() && in PromoteINT_TO_FP()
679 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp189 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
190 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
203 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) { in X86TargetLowering()
204 setCondCodeAction(ISD::SETOEQ, VT, Expand); in X86TargetLowering()
205 setCondCodeAction(ISD::SETUNE, VT, Expand); in X86TargetLowering()
301 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) { in X86TargetLowering()
302 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering()
303 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
337 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
338 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
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DX86InterleavedAccess.cpp233 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
234 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2; in scaleVectorType()
236 VT.getVectorNumElements() / 2); in scaleVectorType()
261 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland() argument
264 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
266 unsigned NumOfElm = VT.getVectorNumElements(); in genShuffleBland()
291 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector() argument
306 genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16, in reorderSubVector()
331 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
342 createUnpackShuffleMask(VT, MaskLowTemp1, true, false); in interleave8bitStride4VF8()
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DX86ISelLowering.h906 MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override { in getScalarShiftAmountTy() argument
938 bool isSafeMemOpType(MVT VT) const override;
942 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
962 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
1000 bool hasBitPreservingFPLogic(EVT VT) const override { in hasBitPreservingFPLogic() argument
1001 return VT == MVT::f32 || VT == MVT::f64 || VT.isVector(); in hasBitPreservingFPLogic()
1045 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
1046 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in shouldTransformSignedTruncationCheck()
1047 VT == MVT::i64; in shouldTransformSignedTruncationCheck()
1058 bool shouldSplatInsEltVarIndex(EVT VT) const override;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp111 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
112 unsigned Size = VT.getSizeInBits().getKnownMinValue(); in RISCVTargetLowering()
124 addRegisterClass(VT, RC); in RISCVTargetLowering()
127 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
128 addRegClassForRVV(VT); in RISCVTargetLowering()
129 for (MVT VT : IntVecVTs) in RISCVTargetLowering() local
130 addRegClassForRVV(VT); in RISCVTargetLowering()
133 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
134 addRegClassForRVV(VT); in RISCVTargetLowering()
137 for (MVT VT : F32VecVTs) in RISCVTargetLowering() local
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DRISCVISelDAGToDAG.cpp57 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
61 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
86 SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); in PreprocessISelDAG()
240 MVT VT = Node->getSimpleValueType(0); in selectVLSEG() local
241 unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); in selectVLSEG()
242 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
268 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG()
270 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
280 MVT VT = Node->getSimpleValueType(0); in selectVLSEGFF() local
282 unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); in selectVLSEGFF()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp38 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
39 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
48 EVT VT = Op.getValueType(); in numBitsUnsigned() local
50 return VT.getSizeInBits() - Known.countMinLeadingZeros(); in numBitsUnsigned()
54 EVT VT = Op.getValueType(); in numBitsSigned() local
58 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op); in numBitsSigned()
134 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
135 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp59 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
61 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
62 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
68 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
69 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
70 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
71 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
72 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
134 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp157 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) { in addTypeForNEON() argument
158 if (VT != PromotedLdStVT) { in addTypeForNEON()
159 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
162 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
166 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
168 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
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DARMFastISel.cpp187 bool isTypeLegal(Type *Ty, MVT &VT);
188 bool isLoadTypeLegal(Type *Ty, MVT &VT);
191 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
194 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
197 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
202 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
203 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
204 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
205 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
206 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/
DLowLevelType.cpp18 LLT::LLT(MVT VT) { in LLT() argument
19 if (VT.isVector()) { in LLT()
20 bool asVector = VT.getVectorNumElements() > 1; in LLT()
22 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
24 } else if (VT.isValid()) { in LLT()
28 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyMachineFunctionInfo.cpp41 for (EVT VT : VTs) { in computeLegalValueVTs() local
42 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT); in computeLegalValueVTs()
43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in computeLegalValueVTs()
114 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
115 Params.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
116 for (auto VT : MFI.getResults()) in WebAssemblyFunctionInfo() local
117 Results.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
144 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
145 addParam(WebAssembly::parseMVT(VT.Value)); in initializeBaseYamlFields()
146 for (auto VT : YamlMFI.Results) in initializeBaseYamlFields() local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp84 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) { in BPFTargetLowering()
85 if (VT == MVT::i32) { in BPFTargetLowering()
89 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom); in BPFTargetLowering()
92 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom); in BPFTargetLowering()
93 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom); in BPFTargetLowering()
94 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom); in BPFTargetLowering()
95 setOperationAction(ISD::ATOMIC_SWAP, VT, Custom); in BPFTargetLowering()
96 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom); in BPFTargetLowering()
99 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
100 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp158 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
160 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
284 SDValue getUNDEF(const SDLoc &DL, EVT VT) const;
287 SDValue convertTo(const SDLoc &DL, EVT VT, SDValue N) const;
631 EVT VT, SDValue &Base, in getAddressOperands() argument
636 Base = CurDAG->getRegister(0, VT); in getAddressOperands()
640 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); in getAddressOperands()
641 } else if (Base.getValueType() != VT) { in getAddressOperands()
643 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && in getAddressOperands()
646 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
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