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Searched refs:VRegs (Results 1 – 25 of 34) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DSwiftErrorValueTracking.cpp181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; in propagateVRegs() local
186 VRegs.push_back(std::make_pair( in propagateVRegs()
204 VRegs.size() >= 1 && in propagateVRegs()
206 VRegs, in propagateVRegs()
208 -> bool { return V.second != VRegs[0].second; }) != in propagateVRegs()
209 VRegs.end(); in propagateVRegs()
214 assert(!VRegs.empty() && in propagateVRegs()
217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); in propagateVRegs()
229 assert(!VRegs.empty() && in propagateVRegs()
234 .addReg(VRegs[0].second); in propagateVRegs()
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DMIRVRegNamerUtils.cpp38 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { in getVRegRenameMap() argument
50 for (const auto &VReg : VRegs) { in getVRegRenameMap()
146 std::vector<NamedVReg> VRegs; in renameInstsInMBB() local
159 VRegs.push_back( in renameInstsInMBB()
163 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false; in renameInstsInMBB()
DMIRVRegNamerUtils.h65 getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
DMachineVerifier.cpp2452 SmallVector<Register, 0> VRegs; member in __anon4126591d0411::FilteringVRegSet
2465 return Filter.filterAndAdd(RS, VRegs); in add()
2467 using const_iterator = decltype(VRegs)::const_iterator;
2468 const_iterator begin() const { return VRegs.begin(); } in begin()
2469 const_iterator end() const { return VRegs.end(); } in end()
2470 size_t size() const { return VRegs.size(); } in size()
2484 FilteringVRegSet VRegs; in calcRegsPassed() local
2488 VRegs.addToFilter(Info.regsKilled); in calcRegsPassed()
2489 VRegs.addToFilter(Info.regsLiveOut); in calcRegsPassed()
2495 VRegs.add(PredInfo.regsLiveOut); in calcRegsPassed()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
DPPCCallLowering.cpp33 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
36 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
38 if (VRegs.size() > 0) in lowerReturn()
52 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
66 ArgInfo OrigArg{VRegs[I], Arg, I}; in lowerFormalArguments()
DPPCCallLowering.h30 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
33 ArrayRef<ArrayRef<Register>> VRegs,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.h38 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
44 ArrayRef<Register> VRegs,
48 ArrayRef<ArrayRef<Register>> VRegs) const;
51 ArrayRef<ArrayRef<Register>> VRegs,
DAMDGPUCallLowering.cpp272 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
288 assert(VRegs.size() == SplitEVTs.size() && in lowerReturnVal()
295 Register Reg = VRegs[i]; in lowerReturnVal()
336 ArrayRef<Register> VRegs, in lowerReturn() argument
344 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
369 insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister); in lowerReturn()
370 else if (!lowerReturnVal(B, Val, VRegs, Ret)) in lowerReturn()
495 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArgumentsKernel()
541 assert(VRegs[i].size() == 1 && in lowerFormalArgumentsKernel()
544 lowerParameterPtr(VRegs[i][0], B, ArgOffset); in lowerFormalArgumentsKernel()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.h36 ArrayRef<Register> VRegs,
40 ArrayRef<ArrayRef<Register>> VRegs,
48 ArrayRef<Register> VRegs,
DARMCallLowering.cpp175 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
189 ArgInfo OrigRetInfo(VRegs, Val->getType(), 0); in lowerReturnVal()
206 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
208 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
214 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret)) in lowerReturn()
356 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
391 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType(), Idx); in lowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/GlSel/
DM68kCallLowering.cpp56 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
69 if (!VRegs.empty()) { in lowerReturn()
71 ArgInfo OrigArg{VRegs, Val->getType(), 0}; in lowerReturn()
86 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
96 ArgInfo OrigArg{VRegs[I], Arg.getType(), I}; in lowerFormalArguments()
DM68kCallLowering.h34 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
38 ArrayRef<ArrayRef<Register>> VRegs,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp133 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
135 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
139 if (!VRegs.empty()) { in lowerReturn()
145 ArgInfo OrigRetInfo(VRegs, Val->getType(), 0); in lowerReturn()
239 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
261 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) in lowerFormalArguments()
264 ArgInfo OrigArg(VRegs[Idx], Arg.getType(), Idx); in lowerFormalArguments()
DX86CallLowering.h32 ArrayRef<Register> VRegs,
36 ArrayRef<ArrayRef<Register>> VRegs,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h439 ArrayRef<Register> VRegs, Register DemoteReg,
445 ArrayRef<Register> VRegs, Register DemoteReg) const;
497 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI, in lowerReturn() argument
501 return lowerReturn(MIRBuilder, Val, VRegs, FLI); in lowerReturn()
509 ArrayRef<Register> VRegs, in lowerReturn() argument
530 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
DLegalizerHelper.h187 SmallVectorImpl<Register> &VRegs);
192 SmallVectorImpl<Register> &VRegs,
237 SmallVectorImpl<Register> &VRegs,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVCallLowering.h31 ArrayRef<Register> VRegs,
35 ArrayRef<ArrayRef<Register>> VRegs,
DRISCVCallLowering.cpp25 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
39 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsCallLowering.h29 ArrayRef<Register> VRegs,
33 ArrayRef<ArrayRef<Register>> VRegs,
DMipsCallLowering.cpp302 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
310 if (!VRegs.empty()) { in lowerReturn()
318 ArgInfo ArgRetInfo(VRegs, *Val, 0); in lowerReturn()
346 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
365 ArgInfo AInfo(VRegs[i], Arg, i); in lowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.h37 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
43 ArrayRef<ArrayRef<Register>> VRegs,
DAArch64CallLowering.cpp337 ArrayRef<Register> VRegs, in lowerReturn() argument
341 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
345 if (!VRegs.empty()) { in lowerReturn()
358 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
365 Register CurVReg = VRegs[i]; in lowerReturn()
518 ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const { in lowerFormalArguments() argument
530 ArgInfo OrigArg{VRegs[i], Arg, i}; in lowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp199 auto *VRegs = VMap.getVRegs(Val); in getOrCreateVRegs() local
211 VRegs->push_back(MRI->createGenericVirtualRegister(Ty)); in getOrCreateVRegs()
212 return *VRegs; in getOrCreateVRegs()
221 llvm::copy(EltRegs, std::back_inserter(*VRegs)); in getOrCreateVRegs()
225 VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0])); in getOrCreateVRegs()
226 bool Success = translate(cast<Constant>(Val), VRegs->front()); in getOrCreateVRegs()
233 return *VRegs; in getOrCreateVRegs()
237 return *VRegs; in getOrCreateVRegs()
352 ArrayRef<Register> VRegs; in translateRet() local
354 VRegs = getOrCreateVRegs(*Ret); in translateRet()
[all …]
DCallLowering.cpp761 ArrayRef<Register> VRegs, Register DemoteReg, in insertSRetLoads() argument
771 assert(VRegs.size() == SplitVTs.size()); in insertSRetLoads()
784 MRI.getType(VRegs[I]), in insertSRetLoads()
786 MIRBuilder.buildLoad(VRegs[I], Addr, *MMO); in insertSRetLoads()
791 ArrayRef<Register> VRegs, in insertSRetStores() argument
801 assert(VRegs.size() == SplitVTs.size()); in insertSRetStores()
815 MRI.getType(VRegs[I]), in insertSRetStores()
817 MIRBuilder.buildStore(VRegs[I], Addr, *MMO); in insertSRetStores()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.h169 SmallVectorImpl<unsigned> &VRegs) const;

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