Home
last modified time | relevance | path

Searched refs:VReg (Results 1 – 25 of 92) sorted by relevance

1234

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() local
38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
46 const Value *Val, Register VReg) { in setCurrentVReg() argument
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg; in setCurrentVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() local
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
[all …]
DMIRVRegNamerUtils.cpp50 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
51 const unsigned Reg = VReg.getReg(); in getVRegRenameMap()
52 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
139 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { in createVirtualRegister() argument
140 assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers"); in createVirtualRegister()
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
142 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
166 unsigned VRegRenamer::createVirtualRegisterWithLowerName(unsigned VReg, in createVirtualRegisterWithLowerName() argument
169 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
171 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName); in createVirtualRegisterWithLowerName()
DLiveRangeEdit.cpp35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createEmptyIntervalFrom() local
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
39 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
57 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
66 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
67 return VReg; in createFrom()
412 unsigned VReg = LI->reg(); in eliminateDeadDefs() local
414 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
424 if (VReg == RegsBeingSpilled[i]) { in eliminateDeadDefs()
[all …]
DRegAllocPBQP.cpp168 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
333 Register VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
604 Register VReg = Worklist.back(); in initializeGraph() local
607 LiveInterval &VRegLI = LIS.getInterval(VReg); in initializeGraph()
617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph()
654 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); in initializeGraph()
659 VRegAllowedMap[VReg.id()] = std::move(VRegAllowed); in initializeGraph()
663 auto VReg = KV.first; in initializeGraph() local
666 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
[all …]
DLiveIntervalUnion.cpp160 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
161 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
162 RecentReg = VReg; in collectInterferingVRegs()
163 InterferingVRegs->push_back(VReg); in collectInterferingVRegs()
DMachineRegisterInfo.cpp172 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister() argument
175 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
176 setType(Reg, getType(VReg)); in cloneVirtualRegister()
182 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType() argument
183 VRegToType.grow(VReg); in setType()
184 VRegToType[VReg] = Ty; in setType()
445 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
447 if (LI.second == VReg) in getLiveInPhysReg()
DMIRVRegNamerUtils.h73 unsigned createVirtualRegister(unsigned VReg);
76 unsigned createVirtualRegisterWithLowerName(unsigned VReg, StringRef Name);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyRegNumbering.cpp92 unsigned VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
94 if (MRI.use_empty(VReg)) in runOnMachineFunction()
97 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " in runOnMachineFunction()
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
103 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) { in runOnMachineFunction()
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); in runOnMachineFunction()
105 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
DWebAssemblyReplacePhysRegs.cpp87 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
91 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
92 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
96 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
98 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
99 << Register::virtReg2Index(VReg) << ")\n"; in runOnMachineFunction()
103 MO.setReg(VReg); in runOnMachineFunction()
DWebAssemblyMachineFunctionInfo.h124 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) { in stackifyVReg() argument
125 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
126 auto I = Register::virtReg2Index(VReg); in stackifyVReg()
131 void unstackifyVReg(unsigned VReg) { in unstackifyVReg() argument
132 auto I = Register::virtReg2Index(VReg); in unstackifyVReg()
136 bool isVRegStackified(unsigned VReg) const { in isVRegStackified() argument
137 auto I = Register::virtReg2Index(VReg); in isVRegStackified()
144 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg() argument
146 auto I = Register::virtReg2Index(VReg); in setWAReg()
150 unsigned getWAReg(unsigned VReg) const { in getWAReg() argument
[all …]
DWebAssemblyRegColoring.cpp67 unsigned VReg) { in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
101 unsigned VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
102 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction()
105 if (MRI->use_empty(VReg)) in runOnMachineFunction()
108 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
110 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h217 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness() argument
218 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
219 return shouldTrackSubRegLiveness(*getRegClass(VReg)); in shouldTrackSubRegLiveness()
728 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
739 void setType(Register VReg, LLT Ty);
765 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint() argument
766 assert(VReg.isVirtual()); in setRegAllocationHint()
767 RegAllocHints[VReg].first = Type; in setRegAllocationHint()
768 RegAllocHints[VReg].second.clear(); in setRegAllocationHint()
769 RegAllocHints[VReg].second.push_back(PrefReg); in setRegAllocationHint()
[all …]
DRegAllocPBQP.h148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg() argument
149 VRegToNodeId[VReg.id()] = NId; in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg() argument
153 auto VRegItr = VRegToNodeId.find(VReg); in getNodeIdForVReg()
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), in NodeMetadata()
202 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg() argument
203 Register getVReg() const { return VReg; } in getVReg()
261 Register VReg; variable
DScheduleDAGInstrs.h57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp282 Register VReg = MRI->createVirtualRegister(RC); in getVR() local
284 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
285 return VReg; in getVR()
308 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
325 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
331 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
332 VReg = NewVReg; in AddRegisterOperand()
362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
383 Register VReg = R->getReg(); in AddOperand() local
395 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
[all …]
DSDNodeDbgValue.h67 return u.VReg; in getVReg()
76 static SDDbgOperand fromVReg(unsigned VReg) { in fromVReg() argument
77 return SDDbgOperand(VReg, VREG); in fromVReg()
109 unsigned VReg; ///< Valid for registers. member
124 u.VReg = VRegOrFrameIdx; in SDDbgOperand()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DInstructionSelect.cpp241 unsigned VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
244 if (!MRI.def_empty(VReg)) in runOnMachineFunction()
245 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
246 else if (!MRI.use_empty(VReg)) in runOnMachineFunction()
247 MI = &*MRI.use_instr_begin(VReg); in runOnMachineFunction()
251 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in runOnMachineFunction()
258 const LLT Ty = MRI.getType(VReg); in runOnMachineFunction()
DUtils.cpp270 Optional<APInt> llvm::getConstantVRegVal(Register VReg, in getConstantVRegVal() argument
273 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); in getConstantVRegVal()
274 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && in getConstantVRegVal()
281 Optional<int64_t> llvm::getConstantVRegSExtVal(Register VReg, in getConstantVRegSExtVal() argument
283 Optional<APInt> Val = getConstantVRegVal(VReg, MRI); in getConstantVRegSExtVal()
290 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, in getConstantVRegValWithLookThrough() argument
315 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && in getConstantVRegValWithLookThrough()
328 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
331 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
332 if (Register::isPhysicalRegister(VReg)) in getConstantVRegValWithLookThrough()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h165 Optional<APInt> getConstantVRegVal(Register VReg,
170 Optional<int64_t> getConstantVRegSExtVal(Register VReg,
177 Register VReg; member
189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
193 const ConstantInt *getConstantIntVRegVal(Register VReg,
195 const ConstantFP* getConstantFPVRegVal(Register VReg,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp562 for (const auto &VReg : YamlMF.VirtualRegisters) { in parseRegisterInfo() local
563 VRegInfo &Info = PFS.getVRegInfo(VReg.ID.Value); in parseRegisterInfo()
565 return error(VReg.ID.SourceRange.Start, in parseRegisterInfo()
567 Twine(VReg.ID.Value) + "'"); in parseRegisterInfo()
570 if (StringRef(VReg.Class.Value).equals("_")) { in parseRegisterInfo()
574 const auto *RC = Target->getRegClass(VReg.Class.Value); in parseRegisterInfo()
579 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo()
582 VReg.Class.SourceRange.Start, in parseRegisterInfo()
584 VReg.Class.Value + "'"); in parseRegisterInfo()
590 if (!VReg.PreferredRegister.Value.empty()) { in parseRegisterInfo()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCMachineFunctionInfo.h243 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) { in addLiveInAttr() argument
244 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); in addLiveInAttr()
249 bool isLiveInSExt(Register VReg) const;
253 bool isLiveInZExt(Register VReg) const;
DPPCMachineFunctionInfo.cpp54 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const { in isLiveInSExt()
56 if (LiveIn.first == VReg) in isLiveInSExt()
61 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const { in isLiveInZExt()
63 if (LiveIn.first == VReg) in isLiveInZExt()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td48 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
49 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
51 VReg vrclass = regclass;
52 VReg wvrclass = wregclass;
53 VReg f8vrclass = f8regclass;
54 VReg f4vrclass = f4regclass;
55 VReg f2vrclass = f2regclass;
146 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
156 class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
163 VReg RegClass = Reg;
[all …]
DRISCVRegisterInfo.td474 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
483 def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
494 def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
505 def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
510 def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
515 def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
519 def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
523 def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
527 def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
539 def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64RegisterBankInfo.cpp772 Register VReg = MI.getOperand(0).getReg(); in getInstrMapping() local
773 if (!VReg) in getInstrMapping()
775 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
823 Register VReg = MI.getOperand(Idx).getReg(); in getInstrMapping() local
824 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
825 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
895 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
896 if (!VReg) in getInstrMapping()
904 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
906 const LLT SrcTy = MRI.getType(VReg); in getInstrMapping()
[all …]

1234