Searched refs:VREV64 (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 203 VREV64, // reverse elements within 64-bit doublewords enumerator
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| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| D | ARMISelLowering.cpp | 1716 MAKE_CASE(ARMISD::VREV64) in getTargetNodeName()
6138 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6620 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
8215 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
8279 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8571 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| D | ARMInstrInfo.td | 269 def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
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| D | ARMInstrNEON.td | 6963 // VREV64 : Vector Reverse elements within 64-bit doublewords
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| /freebsd-12-stable/contrib/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 638 def VREV64 : WOpInst<"vrev64", "..", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
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