Searched refs:VREV32 (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 204 VREV32, // reverse elements within 32-bit words enumerator
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| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| D | ARMISelLowering.cpp | 1717 MAKE_CASE(ARMISD::VREV32) in getTargetNodeName()
8219 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
8573 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
9955 unsigned RevOpcode = NumActiveLanes == 16 ? ARMISD::VREV16 : ARMISD::VREV32; in LowerVecReduce()
17581 unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16; in PerformMVEExtCombine()
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| D | ARMInstrInfo.td | 270 def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
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| D | ARMInstrNEON.td | 6996 // VREV32 : Vector Reverse elements within 32-bit words
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| /freebsd-12-stable/contrib/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 640 def VREV32 : WOpInst<"vrev32", "..", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
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