| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 60 VRC = RC; in Initialize()
157 VRC, MRI, TII); in GetValueInMiddleOfBlock()
191 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
295 Updater->VRC, Updater->MRI, in GetUndefVal()
306 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrVec.td | 442 multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
444 defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>;
446 defm i : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins simm7:$sy)>;
529 multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
532 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
534 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
536 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;
541 multiclass RVDIVm<string opcStr, bits<8>opc, RegisterClass VRC,
544 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
546 defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>;
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoV.td | 149 class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
151 width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1),
210 class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
212 0b000, (outs), (ins VRC:$vs3, GPR:$rs1),
782 multiclass VWholeLoad1<string opcodestr, RegisterClass VRC> {
783 def E8_V : VWholeLoad<0, LSWidth8, opcodestr # "e8.v", VRC>,
785 def E16_V : VWholeLoad<0, LSWidth16, opcodestr # "e16.v", VRC>,
787 def E32_V : VWholeLoad<0, LSWidth32, opcodestr # "e32.v", VRC>,
789 def E64_V : VWholeLoad<0, LSWidth64, opcodestr # "e64.v", VRC>,
793 multiclass VWholeLoad2<string opcodestr, RegisterClass VRC> {
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 44 const TargetRegisterClass *VRC; variable
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 2163 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in hasVGPRs() local
2164 if (!VRC) { in hasVGPRs()
2168 return getCommonSubClass(VRC, RC) != nullptr; in hasVGPRs()
2186 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass() local
2187 assert(VRC && "Invalid register class size"); in getEquivalentVGPRClass()
2188 return VRC; in getEquivalentVGPRClass()
2200 SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
2201 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
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| D | SIInstrInfo.cpp | 4585 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
4587 if (RI.getCommonSubClass(VRC64, VRC)) in legalizeOpWithMove()
4588 VRC = VRC64; in legalizeOpWithMove()
4590 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
4592 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
4993 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
4994 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
4996 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
4998 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
4999 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
[all …]
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| D | SIRegisterInfo.h | 191 getEquivalentSGPRClass(const TargetRegisterClass *VRC) const;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 449 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
450 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
454 if (RC && RC != VRC) in ConstrainForSubReg()
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