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Searched refs:VMX (Results 1 – 18 of 18) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrTDX.td19 // SEAMCALL - Call to SEAM VMX-root Operation Module
23 // SEAMRET - Return to Legacy VMX-root Operation
DX86InstrVMX.td1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
9 // This file describes the instructions that make up the Intel VMX instruction
15 // VMX instructions
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVEInstrInfo.cpp887 Register VMX = VMXl; in expandPostRAPseudo() local
889 VMX = VMXu; in expandPostRAPseudo()
897 .addDef(VMX) in expandPostRAPseudo()
903 .addDef(VMX) in expandPostRAPseudo()
911 .addDef(VMX) in expandPostRAPseudo()
914 .addReg(VMX); in expandPostRAPseudo()
920 .addDef(VMX) in expandPostRAPseudo()
923 .addReg(VMX); in expandPostRAPseudo()
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
DRegisterInfos_ppc64le.h16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
391 } VMX; typedef
DRegisterContextFreeBSD_powerpc.cpp169 } VMX; typedef
DRegisterInfos_powerpc.h14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCScheduleP8.td41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
45 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
DPPCInstrVSX.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1971 2. Shift in the VMX register so that the correct doubleword is correctly
1995 // - Now that we set up the shift amount, we shift in the VMX register
2028 // - Now that we set up the shift amount, we shift in the VMX register
2058 // - Now that we set up the shift amount, we shift in the VMX register
2088 // - Now that we set up the shift amount, we shift in the VMX register
2118 - The shift in the VMX register is by 0/8 for opposite element numbers so
2136 - The shift in the VMX register is by 0/8 for opposite element numbers so
2155 - The shift in the VMX register happens for opposite element numbers
[all …]
DPPCInstrAltivec.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1300 // instructions than VMX instructions)
/freebsd-12-stable/contrib/gcc/config/rs6000/
Dpower4.md370 ; VMX
/freebsd-12-stable/contrib/binutils/include/opcode/
DChangeLog364 * i386.h (i386_optab): Support Intel VMX Instructions.
/freebsd-12-stable/contrib/binutils/opcodes/
DChangeLog-2006191 VMX instructions.
Di386-opc.tbl1295 // VMX instructions.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZScheduleZ13.td1261 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
DSystemZScheduleZ14.td1282 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
DSystemZInstrVector.td581 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>;
DSystemZScheduleZ15.td1318 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
/freebsd-12-stable/contrib/gcc/
DChangeLog-200331515 * config/rs6000/power4.md: Additional VMX bypasses.