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Searched refs:VEX_LIG (Results 1 – 5 of 5) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DX86DisassemblerTables.cpp77 bool VEX_LIG = false, bool VEX_WIG = false, in inheritsFrom() argument
147 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W)) || in inheritsFrom()
149 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); in inheritsFrom()
151 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XS)) || in inheritsFrom()
153 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); in inheritsFrom()
155 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_XD)) || in inheritsFrom()
157 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); in inheritsFrom()
159 return (VEX_LIG && VEX_WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || in inheritsFrom()
161 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)) || in inheritsFrom()
168 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); in inheritsFrom()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrFMA.td323 SchedWriteFMA.Scl>, VEX_LIG;
325 SchedWriteFMA.Scl>, VEX_LIG;
328 SchedWriteFMA.Scl>, VEX_LIG;
330 SchedWriteFMA.Scl>, VEX_LIG;
399 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG,
406 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG,
413 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG,
426 VEX_LIG, FoldGenData<NAME#rr>, Sched<[sched]>;
437 []>, VEX_W, VEX_LIG, Sched<[sched]>;
443 []>, VEX_W, VEX_LIG,
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DX86InstrSSE.td216 VEX_4V, VEX_LIG, VEX_WIG;
221 VEX, VEX_LIG, Sched<[WriteFStore]>, VEX_WIG;
249 VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG;
260 VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG;
864 XS, VEX, VEX_LIG;
868 XS, VEX, VEX_W, VEX_LIG;
872 XD, VEX, VEX_LIG;
876 XD, VEX, VEX_W, VEX_LIG;
881 XS, VEX, VEX_LIG;
885 XS, VEX, VEX_W, VEX_LIG;
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DX86InstrAVX512.td2035 timm:$cc)>, EVEX_4V, VEX_LIG, Sched<[sched]>, SIMD_EXC;
2045 timm:$cc)>, EVEX_4V, VEX_LIG, EVEX_CD8<_.EltSize, CD8VT1>,
2058 EVEX_4V, VEX_LIG, EVEX_B, Sched<[sched]>;
2069 EVEX_4V, VEX_LIG, Sched<[sched]>, SIMD_EXC;
2078 EVEX_4V, VEX_LIG, EVEX_CD8<_.EltSize, CD8VT1>,
2748 sched.Scl, f32x_info, prd>, VEX_LIG,
2751 sched.Scl, f64x_info, prd>, VEX_LIG,
3974 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
3977 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4265 []>, XS, EVEX_4V, VEX_LIG,
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DX86InstrFormats.td227 class VEX_LIG { bit ignoresVEX_L = 1; }