Searched refs:VECREDUCE_FMAX (Results 1 – 13 of 13) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1228 VECREDUCE_FMAX, enumerator
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 489 case ISD::VECREDUCE_FMAX: in LegalizeOp()
893 case ISD::VECREDUCE_FMAX: in Expand()
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| D | SelectionDAGDumper.cpp | 481 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 143 case ISD::VECREDUCE_FMAX: in SoftenFloatResult()
2280 case ISD::VECREDUCE_FMAX: in PromoteFloatResult()
2643 case ISD::VECREDUCE_FMAX: in SoftPromoteHalfResult()
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| D | LegalizeVectorTypes.cpp | 661 case ISD::VECREDUCE_FMAX: in ScalarizeVectorOperand()
2228 case ISD::VECREDUCE_FMAX: in SplitVectorOperand()
4589 case ISD::VECREDUCE_FMAX: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1178 case ISD::VECREDUCE_FMAX: in LegalizeOp()
3764 case ISD::VECREDUCE_FMAX: in ExpandNode()
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| D | SelectionDAG.cpp | 397 case ISD::VECREDUCE_FMAX: in getVecReduceBaseOpcode()
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| D | SelectionDAGBuilder.cpp | 9376 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1739 case ISD::VECREDUCE_FMAX: in visit()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 862 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); in initActions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 607 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in RISCVTargetLowering()
828 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in RISCVTargetLowering()
2497 case ISD::VECREDUCE_FMAX: in LowerOperation()
3864 case ISD::VECREDUCE_FMAX: in getRVVFPReductionOpAndOperands()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1070 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
1290 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
1585 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addTypeForFixedLengthSVE()
4916 case ISD::VECREDUCE_FMAX: in LowerOperation()
10982 case ISD::VECREDUCE_FMAX: in LowerVECREDUCE()
11004 case ISD::VECREDUCE_FMAX: { in LowerVECREDUCE()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 351 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addMVEVectorTypes()
374 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom); in addMVEVectorTypes()
378 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom); in addMVEVectorTypes()
9938 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
10214 case ISD::VECREDUCE_FMAX: in LowerOperation()
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