| /freebsd-12-stable/sys/gnu/dts/mips/ |
| D | A5-V11.dts | 6 compatible = "A5-V11", "ralink,rt5350-soc";
7 model = "A5-V11";
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
|
| D | HexagonRegisterInfo.cpp | 81 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
|
| D | HexagonRegisterInfo.td | 212 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>;
232 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>;
|
| /freebsd-12-stable/sys/gnu/dts/arm/ |
| D | gemini-nas4220b.dts | 126 pins = "V11 GMAC1 TXC";
|
| D | gemini-dlink-dns-313.dts | 240 pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
|
| D | gemini-sq201.dts | 213 pins = "V11 GMAC1 TXC";
|
| D | gemini-sl93512r.dts | 193 pins = "V11 GMAC1 TXEN";
|
| D | gemini-dlink-dir-685.dts | 372 "U8 GMAC0 TXC", "V11 GMAC1 TXC",
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 105 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 237 V8, V9, V10, V11, V12, V13]>>>,
242 V8, V9, V10, V11, V12, V13]>>>,
|
| D | PPCRegisterInfo.td | 373 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
|
| D | PPCISelLowering.cpp | 4243 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4()
4711 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters()
5945 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4()
6547 PPC::V10, PPC::V11, PPC::V12, PPC::V13}; in CC_AIX()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstCombineIntrinsic.cpp | 1547 const APInt &V11 = CI11->getValue(); in instCombineIntrinsic() local
1548 APInt Len = V11.zextOrTrunc(6); in instCombineIntrinsic()
1549 APInt Idx = V11.lshr(8).zextOrTrunc(6); in instCombineIntrinsic()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| D | VEDisassembler.cpp | 100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 579 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, in DecodeHvxVRRegisterClass()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 7000 RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
8619 .Case("{v11}", RISCV::V11) in getRegForInlineAsmConstraint()
|