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Searched refs:UndefReg (Results 1 – 8 of 8) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anone22aadcf0111::RegSeqInfo
61 UndefReg.push_back(Chan); in RegSeqInfo()
162 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
165 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++])); in tryMergeVector()
192 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
299 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
DSIOptimizeVGPRLiveRange.cpp480 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
487 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeLiveRange()
521 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
537 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeWaterfallLiveRange()
DSILowerI1Copies.cpp428 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local
430 UndefReg); in insertUndefLaneMask()
431 return UndefReg; in insertUndefLaneMask()
DAMDGPUInstructionSelector.cpp2044 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2045 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2049 .addReg(UndefReg) in selectG_SZA_EXT()
2103 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2106 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2110 .addReg(UndefReg) in selectG_SZA_EXT()
DSIISelLowering.cpp11187 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
11190 UndefReg, Src0, SDValue()); in PostISelFolding()
11204 Src0 = UndefReg; in PostISelFolding()
11205 Src1 = UndefReg; in PostISelFolding()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallFrameOptimization.cpp543 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
547 .addReg(UndefReg) in adjustCallSequence()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp312 Register UndefReg; in matchCombineShuffleVector() local
316 if (!UndefReg) { in matchCombineShuffleVector()
318 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
320 Ops.push_back(UndefReg); in matchCombineShuffleVector()
2890 Register UndefReg; in applyCombineInsertVecElts() local
2892 if (UndefReg) in applyCombineInsertVecElts()
2893 return UndefReg; in applyCombineInsertVecElts()
2895 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2896 return UndefReg; in applyCombineInsertVecElts()
DLegalizerHelper.cpp1515 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
1517 Unmerges.push_back(UndefReg); in widenScalarMergeValues()