Searched refs:TmpR1 (Results 1 – 2 of 2) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1854 Register TmpR1 = MRI.createVirtualRegister(RC); in expandStoreVecPred() local
1859 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1) in expandStoreVecPred()
1864 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI); in expandStoreVecPred()
1868 NewRegs.push_back(TmpR1); in expandStoreVecPred()
1889 Register TmpR1 = MRI.createVirtualRegister(RC); in expandLoadVecPred() local
1895 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI); in expandLoadVecPred()
1899 .addReg(TmpR1, RegState::Kill) in expandLoadVecPred()
1903 NewRegs.push_back(TmpR1); in expandLoadVecPred()
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| D | HexagonSplitDouble.cpp | 953 Register TmpR1 = MRI->createVirtualRegister(IntRC); in splitAslOr() local
954 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1) in splitAslOr()
961 .addReg(TmpR1); in splitAslOr()
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