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Searched refs:TargetOpcode (Results 1 – 25 of 226) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64RegisterBankInfo.cpp291 case TargetOpcode::G_OR: { in getInstrAlternativeMappings()
314 case TargetOpcode::G_BITCAST: { in getInstrAlternativeMappings()
350 case TargetOpcode::G_LOAD: { in getInstrAlternativeMappings()
387 case TargetOpcode::G_OR: in applyMappingImpl()
388 case TargetOpcode::G_BITCAST: in applyMappingImpl()
389 case TargetOpcode::G_LOAD: in applyMappingImpl()
404 case TargetOpcode::G_FADD: in isPreISelGenericFloatingPointOpcode()
405 case TargetOpcode::G_FSUB: in isPreISelGenericFloatingPointOpcode()
406 case TargetOpcode::G_FMUL: in isPreISelGenericFloatingPointOpcode()
407 case TargetOpcode::G_FMA: in isPreISelGenericFloatingPointOpcode()
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DAArch64InstructionSelector.cpp617 MIB.buildInstr(TargetOpcode::REG_SEQUENCE, {DesiredClass}, {}); in createTuple()
722 case TargetOpcode::G_SHL: in selectBinaryOp()
724 case TargetOpcode::G_LSHR: in selectBinaryOp()
726 case TargetOpcode::G_ASHR: in selectBinaryOp()
733 case TargetOpcode::G_PTR_ADD: in selectBinaryOp()
735 case TargetOpcode::G_SHL: in selectBinaryOp()
737 case TargetOpcode::G_LSHR: in selectBinaryOp()
739 case TargetOpcode::G_ASHR: in selectBinaryOp()
750 case TargetOpcode::G_FADD: in selectBinaryOp()
752 case TargetOpcode::G_FSUB: in selectBinaryOp()
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DAArch64PostLegalizerCombiner.cpp64 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
76 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
79 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
86 std::get<0>(MatchInfo) = TargetOpcode::G_FADD; in matchExtractVecEltPairwiseAdd()
98 assert(Opc == TargetOpcode::G_FADD && "Unexpected opcode!"); in applyExtractVecEltPairwiseAdd()
114 return Opc == TargetOpcode::G_SEXT || Opc == TargetOpcode::G_SEXT_INREG; in isSignExtended()
119 return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT; in isZeroExtended()
125 assert(MI.getOpcode() == TargetOpcode::G_MUL); in matchAArch64MulConstCombine()
162 if (UseOpc == TargetOpcode::G_ADD || UseOpc == TargetOpcode::G_PTR_ADD || in matchAArch64MulConstCombine()
163 UseOpc == TargetOpcode::G_SUB) in matchAArch64MulConstCombine()
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DAArch64PreLegalizerCombiner.cpp39 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT); in matchFConstantToConstant()
54 assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT); in applyFConstantToConstant()
66 assert(MI.getOpcode() == TargetOpcode::G_ICMP && KB); in matchICmpRedundantTrunc()
97 assert(MI.getOpcode() == TargetOpcode::G_ICMP); in applyICmpRedundantTrunc()
118 assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE); in matchFoldGlobalOffset()
147 if (UseInstr.getOpcode() != TargetOpcode::G_PTR_ADD) in matchFoldGlobalOffset()
271 case TargetOpcode::G_CONCAT_VECTORS: in combine()
273 case TargetOpcode::G_SHUFFLE_VECTOR: in combine()
275 case TargetOpcode::G_MEMCPY_INLINE: in combine()
277 case TargetOpcode::G_MEMCPY: in combine()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp60 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
73 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
85 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue()
121 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
130 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
140 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
153 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
161 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
189 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}); in buildPtrAdd()
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DGISelKnownBits.cpp38 case TargetOpcode::COPY: in computeKnownAlignment()
40 case TargetOpcode::G_FRAME_INDEX: { in computeKnownAlignment()
44 case TargetOpcode::G_INTRINSIC: in computeKnownAlignment()
45 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: in computeKnownAlignment()
179 case TargetOpcode::G_BUILD_VECTOR: { in computeKnownBitsImpl()
198 case TargetOpcode::COPY: in computeKnownBitsImpl()
199 case TargetOpcode::G_PHI: in computeKnownBitsImpl()
200 case TargetOpcode::PHI: { in computeKnownBitsImpl()
233 Depth + (Opcode != TargetOpcode::COPY)); in computeKnownBitsImpl()
247 case TargetOpcode::G_CONSTANT: { in computeKnownBitsImpl()
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DLegalizerHelper.cpp114 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || in legalizeInstrStep()
115 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) in legalizeInstrStep()
236 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); in getUnmergeResults()
281 if (PadStrategy == TargetOpcode::G_ZEXT) in buildLCMMergePieces()
283 else if (PadStrategy == TargetOpcode::G_ANYEXT) in buildLCMMergePieces()
286 assert(PadStrategy == TargetOpcode::G_SEXT); in buildLCMMergePieces()
328 if (PadStrategy == TargetOpcode::G_ANYEXT) in buildLCMMergePieces()
330 else if (PadStrategy == TargetOpcode::G_ZEXT) in buildLCMMergePieces()
423 case TargetOpcode::G_SDIV: in getRTLibDesc()
425 case TargetOpcode::G_UDIV: in getRTLibDesc()
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DUtils.cpp65 TII.get(TargetOpcode::COPY), ConstrainedReg) in constrainOperandRegClass()
70 TII.get(TargetOpcode::COPY), Reg) in constrainOperandRegClass()
201 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) in isTriviallyDead()
204 if (MI.getOpcode() == TargetOpcode::LIFETIME_START || in isTriviallyDead()
205 MI.getOpcode() == TargetOpcode::LIFETIME_END) in isTriviallyDead()
295 return Opcode == TargetOpcode::G_CONSTANT || in getConstantVRegValWithLookThrough()
296 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); in getConstantVRegValWithLookThrough()
318 case TargetOpcode::G_ANYEXT: in getConstantVRegValWithLookThrough()
322 case TargetOpcode::G_TRUNC: in getConstantVRegValWithLookThrough()
323 case TargetOpcode::G_SEXT: in getConstantVRegValWithLookThrough()
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DCombinerHelper.cpp154 if (MI.getOpcode() != TargetOpcode::COPY) in matchCombineCopy()
179 assert(MI.getOpcode() == TargetOpcode::G_CONCAT_VECTORS && in matchCombineConcatVectors()
192 case TargetOpcode::G_BUILD_VECTOR: in matchCombineConcatVectors()
199 case TargetOpcode::G_IMPLICIT_DEF: { in matchCombineConcatVectors()
255 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && in matchCombineShuffleVector()
354 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
366 if (OpcodeForCandidate == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
367 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
369 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
370 OpcodeForCandidate != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
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DCSEInfo.cpp41 case TargetOpcode::G_ADD: in shouldCSEOpc()
42 case TargetOpcode::G_AND: in shouldCSEOpc()
43 case TargetOpcode::G_ASHR: in shouldCSEOpc()
44 case TargetOpcode::G_LSHR: in shouldCSEOpc()
45 case TargetOpcode::G_MUL: in shouldCSEOpc()
46 case TargetOpcode::G_OR: in shouldCSEOpc()
47 case TargetOpcode::G_SHL: in shouldCSEOpc()
48 case TargetOpcode::G_SUB: in shouldCSEOpc()
49 case TargetOpcode::G_XOR: in shouldCSEOpc()
50 case TargetOpcode::G_UDIV: in shouldCSEOpc()
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DCSEMIRBuilder.cpp174 case TargetOpcode::G_ADD: in buildInstr()
175 case TargetOpcode::G_AND: in buildInstr()
176 case TargetOpcode::G_ASHR: in buildInstr()
177 case TargetOpcode::G_LSHR: in buildInstr()
178 case TargetOpcode::G_MUL: in buildInstr()
179 case TargetOpcode::G_OR: in buildInstr()
180 case TargetOpcode::G_SHL: in buildInstr()
181 case TargetOpcode::G_SUB: in buildInstr()
182 case TargetOpcode::G_XOR: in buildInstr()
183 case TargetOpcode::G_UDIV: in buildInstr()
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DIRTranslator.cpp317 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder); in translateFNeg()
1452 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder); in translateBitCast()
1610 if (Opcode != TargetOpcode::G_MEMCPY_INLINE) { in translateMemFunc()
1622 if (Opcode != TargetOpcode::G_MEMSET) in translateMemFunc()
1635 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
1678 return TargetOpcode::G_BSWAP; in getSimpleIntrinsicOpcode()
1680 return TargetOpcode::G_BITREVERSE; in getSimpleIntrinsicOpcode()
1682 return TargetOpcode::G_FSHL; in getSimpleIntrinsicOpcode()
1684 return TargetOpcode::G_FSHR; in getSimpleIntrinsicOpcode()
1686 return TargetOpcode::G_FCEIL; in getSimpleIntrinsicOpcode()
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DLegacyLegalizerInfo.cpp71 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
72 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
73 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
74 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
75 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegacyLegalizerInfo()
77 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
78 setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}}); in LegacyLegalizerInfo()
81 TargetOpcode::G_IMPLICIT_DEF, 0, narrowToSmallerAndUnsupportedIfTooSmall); in LegacyLegalizerInfo()
83 TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest); in LegacyLegalizerInfo()
85 TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest); in LegacyLegalizerInfo()
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DGenericMachineInstrs.h66 case TargetOpcode::G_LOAD: in classof()
67 case TargetOpcode::G_STORE: in classof()
68 case TargetOpcode::G_ZEXTLOAD: in classof()
69 case TargetOpcode::G_SEXTLOAD: in classof()
85 case TargetOpcode::G_LOAD: in classof()
86 case TargetOpcode::G_ZEXTLOAD: in classof()
87 case TargetOpcode::G_SEXTLOAD: in classof()
99 return MI->getOpcode() == TargetOpcode::G_LOAD; in classof()
107 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD || in classof()
108 MI->getOpcode() == TargetOpcode::G_ZEXTLOAD; in classof()
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DMIPatternMatch.h296 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
298 return BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>(L, R);
302 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_PTR_ADD, true>
304 return BinaryOp_match<LHS, RHS, TargetOpcode::G_PTR_ADD, true>(L, R);
308 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB> m_GSub(const LHS &L,
310 return BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB>(L, R);
314 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>
316 return BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>(L, R);
320 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>
322 return BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>(L, R);
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DUtils.h50 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
51 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
52 case TargetOpcode::G_VECREDUCE_FADD: \
53 case TargetOpcode::G_VECREDUCE_FMUL: \
54 case TargetOpcode::G_VECREDUCE_FMAX: \
55 case TargetOpcode::G_VECREDUCE_FMIN: \
56 case TargetOpcode::G_VECREDUCE_ADD: \
57 case TargetOpcode::G_VECREDUCE_MUL: \
58 case TargetOpcode::G_VECREDUCE_AND: \
59 case TargetOpcode::G_VECREDUCE_OR: \
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DMachineIRBuilder.h481 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
514 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); in buildUAddo()
520 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); in buildUSubo()
526 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1}); in buildSAddo()
532 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1}); in buildSSubo()
552 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
560 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
568 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
576 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
612 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)}); in buildSExtInReg()
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DLegalizationArtifactCombiner.h38 case TargetOpcode::G_TRUNC: in isArtifactCast()
39 case TargetOpcode::G_SEXT: in isArtifactCast()
40 case TargetOpcode::G_ZEXT: in isArtifactCast()
41 case TargetOpcode::G_ANYEXT: in isArtifactCast()
56 assert(MI.getOpcode() == TargetOpcode::G_ANYEXT); in tryCombineAnyExt()
87 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineAnyExt()
89 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) { in tryCombineAnyExt()
105 assert(MI.getOpcode() == TargetOpcode::G_ZEXT); in tryCombineZExt()
118 if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || in tryCombineZExt()
147 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineZExt()
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DIRTranslator.h412 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); in translateAdd()
415 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); in translateSub()
418 return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder); in translateAnd()
421 return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder); in translateMul()
424 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); in translateOr()
427 return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder); in translateXor()
431 return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder); in translateUDiv()
434 return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder); in translateSDiv()
437 return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder); in translateURem()
440 return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder); in translateSRem()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsRegisterBankInfo.cpp111 case TargetOpcode::G_FCONSTANT: in isFloatingPointOpcode()
112 case TargetOpcode::G_FADD: in isFloatingPointOpcode()
113 case TargetOpcode::G_FSUB: in isFloatingPointOpcode()
114 case TargetOpcode::G_FMUL: in isFloatingPointOpcode()
115 case TargetOpcode::G_FDIV: in isFloatingPointOpcode()
116 case TargetOpcode::G_FABS: in isFloatingPointOpcode()
117 case TargetOpcode::G_FSQRT: in isFloatingPointOpcode()
118 case TargetOpcode::G_FCEIL: in isFloatingPointOpcode()
119 case TargetOpcode::G_FFLOOR: in isFloatingPointOpcode()
120 case TargetOpcode::G_FPEXT: in isFloatingPointOpcode()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp169 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) { in getInstrMapping()
176 case TargetOpcode::G_ADD: in getInstrMapping()
177 case TargetOpcode::G_SUB: in getInstrMapping()
178 case TargetOpcode::G_MUL: in getInstrMapping()
180 case TargetOpcode::G_FADD: in getInstrMapping()
181 case TargetOpcode::G_FSUB: in getInstrMapping()
182 case TargetOpcode::G_FMUL: in getInstrMapping()
183 case TargetOpcode::G_FDIV: in getInstrMapping()
185 case TargetOpcode::G_SHL: in getInstrMapping()
186 case TargetOpcode::G_LSHR: in getInstrMapping()
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DX86InstructionSelector.cpp256 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectCopy()
321 if (Opcode == TargetOpcode::LOAD_STACK_GUARD) in select()
342 case TargetOpcode::G_STORE: in select()
343 case TargetOpcode::G_LOAD: in select()
345 case TargetOpcode::G_PTR_ADD: in select()
346 case TargetOpcode::G_FRAME_INDEX: in select()
348 case TargetOpcode::G_GLOBAL_VALUE: in select()
350 case TargetOpcode::G_CONSTANT: in select()
352 case TargetOpcode::G_FCONSTANT: in select()
354 case TargetOpcode::G_PTRTOINT: in select()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
52 case TargetOpcode::DBG_LABEL: in doesNotGeneratecode()
63 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); in runOnMachineFunction()
83 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetOpcodes.h20 namespace TargetOpcode {
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
DMachineInstr.h1188 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1189 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1191 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1200 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1204 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1211 return getOpcode() == TargetOpcode::DBG_VALUE;
1214 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1219 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1220 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1221 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
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