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Searched refs:TRN1 (Results 1 – 7 of 7) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h180 TRN1, enumerator
DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2335 (instregex "(TRN1|TRN2)(v4i32|v8i16|v16i8)")>;
2341 (instregex "(TRN1|TRN2)(v2i32|v4i16|v8i8)")>;
DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
DAArch64SchedThunderX3T110.td1631 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^TRN1", "^TRN2")>;
DAArch64ISelLowering.cpp1976 MAKE_CASE(AArch64ISD::TRN1) in getTargetNodeName()
3928 return DAG.getNode(AArch64ISD::TRN1, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9201 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
9439 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; in LowerVECTOR_SHUFFLE()
9452 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; in LowerVECTOR_SHUFFLE()
DAArch64SchedA64FX.td1934 def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^TRN1", "^TRN2")>;
DAArch64InstrInfo.td486 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
5183 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;