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Searched refs:Subtarget (Results 1 – 25 of 251) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
26 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
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DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
142 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
162 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop()
164 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
173 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
178 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy()
192 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
203 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
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DARMISelLowering.cpp456 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
457 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
458 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
463 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() && in ARMTargetLowering()
464 !Subtarget->isTargetWatchOS()) { in ARMTargetLowering()
472 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
474 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() && in ARMTargetLowering()
475 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
549 if (Subtarget->isAAPCS_ABI() && in ARMTargetLowering()
550 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || in ARMTargetLowering()
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DARMFastISel.cpp110 const ARMSubtarget *Subtarget; member in __anone109c5480111::ARMFastISel
125 Subtarget( in ARMFastISel()
128 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), in ARMFastISel()
129 TLI(*Subtarget->getTargetLowering()) { in ARMFastISel()
438 if (!Subtarget->hasVFP2Base()) return false; in ARMMaterializeFP()
461 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { in ARMMaterializeInt()
473 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()
490 if (Subtarget->useMovt()) in ARMMaterializeInt()
528 if (Subtarget->isROPI() || Subtarget->isRWPI()) in ARMMaterializeGV()
531 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV); in ARMMaterializeGV()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsRegisterInfo.cpp94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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DMipsISelLowering.cpp117 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 in getRegisterTypeForCallingConv()
125 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); in getNumRegistersForCallingConv()
300 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { in MipsTargetLowering()
307 if (Subtarget.hasMips32r6()) in MipsTargetLowering()
360 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { in MipsTargetLowering()
365 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
380 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
387 if (Subtarget.isGP64bit()) in MipsTargetLowering()
413 if (Subtarget.hasCnMips()) { in MipsTargetLowering()
427 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
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DMipsAsmPrinter.cpp79 Subtarget = &MF.getSubtarget<MipsSubtarget>(); in runOnMachineFunction()
82 if (Subtarget->inMips16Mode()) in runOnMachineFunction()
96 if (Subtarget->isTargetNaCl()) in runOnMachineFunction()
118 bool InMicroMipsMode = Subtarget->inMicroMipsMode(); in emitPseudoIndirectBranch()
121 if (Subtarget->hasMips64r6()) { in emitPseudoIndirectBranch()
125 } else if (Subtarget->hasMips32r6()) { in emitPseudoIndirectBranch()
133 } else if (Subtarget->inMicroMipsMode()) in emitPseudoIndirectBranch()
144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch()
165 const MipsSubtarget &Subtarget) { in emitDirectiveRelocJalr() argument
179 Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", in emitDirectiveRelocJalr()
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DMipsSEISelLowering.cpp70 if (Subtarget.isGP64bit()) in MipsSETargetLowering()
73 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { in MipsSETargetLowering()
85 if (Subtarget.hasDSP()) { in MipsSETargetLowering()
108 if (Subtarget.hasMips32r2()) { in MipsSETargetLowering()
114 if (Subtarget.hasDSPR2()) in MipsSETargetLowering()
117 if (Subtarget.hasMSA()) { in MipsSETargetLowering()
171 if (!Subtarget.useSoftFloat()) { in MipsSETargetLowering()
175 if (!Subtarget.isSingleFloat()) { in MipsSETargetLowering()
176 if (Subtarget.isFP64bit()) in MipsSETargetLowering()
188 if (Subtarget.hasCnMips()) in MipsSETargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCLowerMASSVEntries.cpp52 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
54 const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
73 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) { in getCPUSuffix() argument
75 if (!Subtarget) in getCPUSuffix()
78 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
80 if (Subtarget->hasP9Vector()) in getCPUSuffix()
82 if (Subtarget->hasP8Vector()) in getCPUSuffix()
84 if (Subtarget->isAIXABI()) in getCPUSuffix()
96 const PPCSubtarget *Subtarget) { in createMASSVFuncName() argument
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DPPCRegisterInfo.cpp164 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
166 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs()
168 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
169 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
173 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs()
174 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
189 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs()
193 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
196 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
203 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
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DPPCFrameLowering.cpp84 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
85 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
86 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
87 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
88 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering()
89 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering()
230 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
235 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
240 assert(Subtarget.isAIXABI() && "Unexpected ABI."); in getCalleeSavedSpillSlots()
242 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
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DPPCISelLowering.cpp145 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
152 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
161 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
186 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
216 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
232 if (Subtarget.useCRBits()) { in PPCTargetLowering()
235 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
309 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
344 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
349 if (Subtarget.hasVSX()) { in PPCTargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPU.td27 // Subtarget Features (device properties)
643 // Subtarget Features (options and debugging)
1214 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1218 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1219 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1223 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1224 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1225 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1229 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1233 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCV.td18 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
25 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
32 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
40 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
48 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
55 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
62 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
65 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
70 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
77 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
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DRISCVISelLowering.cpp47 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
49 if (Subtarget.isRV32E()) in RISCVTargetLowering()
52 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
56 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
60 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
62 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
66 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
81 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
88 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { in EmitTargetCodeForMemset()
121 if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned in EmitTargetCodeForMemset()
154 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
185 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs() argument
188 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
207 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB() argument
210 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
215 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
227 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
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DX86ISelLowering.cpp116 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
117 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
118 X86ScalarSSEf64 = Subtarget.hasSSE2(); in X86TargetLowering()
119 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
132 if (Subtarget.isAtom()) in X86TargetLowering()
134 else if (Subtarget.is64Bit()) in X86TargetLowering()
138 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
143 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
145 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
150 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) { in X86TargetLowering()
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DX86RegisterInfo.cpp121 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getLargestLegalSuperClass() local
130 if (!Subtarget.hasAVX512() && in getLargestLegalSuperClass()
137 if (!Subtarget.hasVLX() && in getLargestLegalSuperClass()
144 if (Subtarget.hasVLX() && in getLargestLegalSuperClass()
151 if (Subtarget.hasAVX512() && in getLargestLegalSuperClass()
177 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getPointerRegClass() local
181 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
197 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
202 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
206 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
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DX86FastISel.cpp50 const X86Subtarget *Subtarget; member in __anonea3157140111::X86FastISel
63 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel()
64 X86ScalarSSEf64 = Subtarget->hasSSE2(); in X86FastISel()
65 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
139 return Subtarget->getInstrInfo(); in getInstrInfo()
325 bool HasSSE41 = Subtarget->hasSSE41(); in X86FastEmitLoad()
326 bool HasAVX = Subtarget->hasAVX(); in X86FastEmitLoad()
327 bool HasAVX2 = Subtarget->hasAVX2(); in X86FastEmitLoad()
328 bool HasAVX512 = Subtarget->hasAVX512(); in X86FastEmitLoad()
329 bool HasVLX = Subtarget->hasVLX(); in X86FastEmitLoad()
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DX86LoadValueInjectionRetHardening.cpp63 const X86Subtarget *Subtarget = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
64 if (!Subtarget->useLVIControlFlowIntegrity() || !Subtarget->is64Bit()) in runOnMachineFunction()
73 const X86RegisterInfo *TRI = Subtarget->getRegisterInfo(); in runOnMachineFunction()
74 const X86InstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
DX86LegalizerInfo.cpp61 : Subtarget(STI), TM(TM) { in X86LegalizerInfo()
146 if (!Subtarget.is64Bit()) { in setLegalizerInfo32bit()
202 if (!Subtarget.is64Bit()) in setLegalizerInfo64bit()
292 if (!Subtarget.hasSSE1()) in setLegalizerInfoSSE1()
325 if (!Subtarget.hasSSE2()) in setLegalizerInfoSSE2()
377 if (!Subtarget.hasSSE41()) in setLegalizerInfoSSE41()
388 if (!Subtarget.hasAVX()) in setLegalizerInfoAVX()
435 if (!Subtarget.hasAVX2()) in setLegalizerInfoAVX2()
471 if (!Subtarget.hasAVX512()) in setLegalizerInfoAVX512()
511 if (!Subtarget.hasVLX()) in setLegalizerInfoAVX512()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
67 if (!Subtarget.is64Bit()) in getReservedRegs()
82 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
90 if (!Subtarget.isV9()) { in getReservedRegs()
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
182 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
196 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
DWebAssemblyUtilities.cpp101 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFunctionTableSymbol() argument
114 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFunctionTableSymbol()
120 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFuncrefCallTableSymbol() argument
139 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFuncrefCallTableSymbol()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
198 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
202 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
220 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
224 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
239 const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs()
249 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
250 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp95 const AArch64Subtarget &Subtarget; member
107 Subtarget(Subtarget_), IsReturn(IsReturn) {} in AArch64OutgoingValueAssigner()
113 bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv()); in assignArg()
231 Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {} in OutgoingArgHandler()
326 const AArch64Subtarget &Subtarget; member
348 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); in lowerReturn() local
441 AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget, in lowerReturn()
556 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); in lowerFormalArguments() local
557 if (!Subtarget.isTargetDarwin()) { in lowerFormalArguments()
565 alignTo(Assigner.StackOffset, Subtarget.isTargetILP32() ? 4 : 8); in lowerFormalArguments()
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