| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1274 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local
1281 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR()
1291 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1299 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
1320 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, in SplitVecRes_INSERT_SUBVECTOR()
2388 SDValue SubVec = N->getOperand(1); in SplitVecOp_INSERT_SUBVECTOR() local
2393 GetSplitVector(SubVec, Lo, Hi); in SplitVecOp_INSERT_SUBVECTOR()
4853 SDValue SubVec = N->getOperand(1); in WidenVecOp_INSERT_SUBVECTOR() local
4859 if (getTypeAction(SubVec.getValueType()) == TargetLowering::TypeWidenVector) in WidenVecOp_INSERT_SUBVECTOR()
4860 SubVec = GetWidenedVector(SubVec); in WidenVecOp_INSERT_SUBVECTOR()
[all …]
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| D | LegalizeIntegerTypes.cpp | 4763 SDValue SubVec = N->getOperand(1); in PromoteIntRes_INSERT_SUBVECTOR() local
4766 EVT SubVecVT = SubVec.getValueType(); in PromoteIntRes_INSERT_SUBVECTOR()
4772 SubVec = DAG.getNode(ISD::ANY_EXTEND, dl, NSubVT, SubVec); in PromoteIntRes_INSERT_SUBVECTOR()
4774 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
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| D | SelectionDAGBuilder.cpp | 7161 SDValue SubVec = getValue(I.getOperand(1)); in visitIntrinsicCall() local
7172 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
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| D | DAGCombiner.cpp | 18438 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local
18440 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle()
18473 ConcatOps[0] = SubVec; in combineInsertEltToShuffle()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 6152 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
6157 if (SubVec.isUndef()) in insert1BitVector()
6178 SubVec, Idx); in insert1BitVector()
6182 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector()
6198 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6200 SubVec, ZeroIdx); in insert1BitVector()
6201 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
6205 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6206 Undef, SubVec, ZeroIdx); in insert1BitVector()
6210 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCalls.cpp | 1893 Value *SubVec = II->getArgOperand(1); in visitCallInst() local
1897 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst()
1909 return replaceInstUsesWith(CI, SubVec); in visitCallInst()
1922 Value *WidenShuffle = Builder.CreateShuffleVector(SubVec, WidenMask); in visitCallInst()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 3904 SDValue SubVec = Op.getOperand(1); in lowerINSERT_SUBVECTOR() local
3906 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR()
3933 SubVec = DAG.getBitcast(SubVecVT, SubVec); in lowerINSERT_SUBVECTOR()
3942 SubVec = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtSubVecVT, SubVec); in lowerINSERT_SUBVECTOR()
3943 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
3963 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
3964 DAG.getUNDEF(ContainerVT), SubVec, in lowerINSERT_SUBVECTOR()
3974 SubVec, SlideupAmt, Mask, VL); in lowerINSERT_SUBVECTOR()
4033 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR()
4034 DAG.getUNDEF(InterSubVT), SubVec, in lowerINSERT_SUBVECTOR()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | IRBuilder.h | 927 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
930 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8923 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local
8927 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR()
8933 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec, in LowerEXTRACT_SUBVECTOR()
15589 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local
15592 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(), in PerformTruncatingStoreCombine()
20451 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local
20455 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad()
20456 SubVec, in lowerInterleavedLoad()
20459 SubVecs[SV].push_back(SubVec); in lowerInterleavedLoad()
20468 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 11763 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local
11767 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad()
11768 SubVec, FixedVectorType::get(SVI->getType()->getElementType(), in lowerInterleavedLoad()
11770 SubVecs[SVI].push_back(SubVec); in lowerInterleavedLoad()
11779 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
11781 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; in lowerInterleavedLoad()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| D | Verifier.cpp | 5234 Value *SubVec = Call.getArgOperand(1); in visitIntrinsicCall() local
5239 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 5891 Value *SubVec = Call->getArgOperand(1); in simplifyIntrinsic() local
5899 if (match(SubVec, m_Intrinsic<Intrinsic::experimental_vector_extract>( in simplifyIntrinsic()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 5607 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local
5610 Pieces.push_back(SubVec); in lowerVECTOR_SHUFFLE()
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