Searched refs:SrcOp2 (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1826 unsigned SrcOp2 = 0; in buildAliasResultOperands() local
1837 SrcOp2 = findAsmOperandNamed(Name, Insert.first->second); in buildAliasResultOperands()
1842 Insert.first->second = SrcOp2; in buildAliasResultOperands()
1846 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1858 SrcOp2 = findAsmOperand(Name, SubIdx); in buildAliasResultOperands()
1860 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1862 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2156 uint8_t SrcOp2 = in emitConvertFuncs() local
2161 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
2166 ConversionRow.push_back(SrcOp2); in emitConvertFuncs()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1805 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1811 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 18464 auto SrcOp2 = Op.getOperand(1); in LowerFixedLengthConcatVectorsToSVE() local
18482 SrcOp2 = convertToScalableVector(DAG, ContainerVT, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
18484 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
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