Searched refs:SrcOp1 (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1825 unsigned SrcOp1 = 0; in buildAliasResultOperands() local
1832 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1835 StringRef Name = AsmOperands[SrcOp1].SrcOpName; in buildAliasResultOperands()
1836 auto Insert = OperandRefs.try_emplace(Name, SrcOp1); in buildAliasResultOperands()
1846 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1855 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1860 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1862 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2154 uint8_t SrcOp1 = in emitConvertFuncs() local
2161 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1804 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment() local
1809 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; in getShuffleComment()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 18463 auto SrcOp1 = Op.getOperand(0); in LowerFixedLengthConcatVectorsToSVE() local
18466 EVT SrcVT = SrcOp1.getValueType(); in LowerFixedLengthConcatVectorsToSVE()
18481 SrcOp1 = convertToScalableVector(DAG, ContainerVT, SrcOp1); in LowerFixedLengthConcatVectorsToSVE()
18484 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
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