| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| D | AArch64SchedA55.td | 65 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
194 // Shifted operand
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| D | AArch64SchedA57.td | 141 // Shifted Register with Shift == 0
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/Tooling/ASTDiff/ |
| D | ASTDiff.cpp | 150 int findPositionInParent(NodeId Id, bool Shifted = false) const;
339 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const { in findPositionInParent()
346 if (Shifted) in findPositionInParent()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 2387 unsigned Shifted = 0; in alignToARMConstant() local
2394 Shifted += 2; in alignToARMConstant()
2403 if (Shifted > 24) in alignToARMConstant()
2404 Value = Value >> (Shifted - 24); in alignToARMConstant()
2406 Value = Value << (24 - Shifted); in alignToARMConstant()
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| D | ARMScheduleM7.td | 322 // Shifted ALU operands are read a cycle early.
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| D | ARMInstrThumb2.td | 54 // Shifted operands. No register controlled shifts for Thumb2.
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstCombineIntrinsic.cpp | 1007 Value *Shifted = IC.Builder.CreateLShr(Masked, in instCombineIntrinsic() local
1010 return IC.replaceInstUsesWith(II, Shifted); in instCombineIntrinsic()
1051 Value *Shifted = IC.Builder.CreateShl(Input, in instCombineIntrinsic() local
1054 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic()
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| D | X86ISelLowering.cpp | 27238 SDValue Shifted = in LowerSET_ROUNDING() local
27241 RMBits = DAG.getNode(ISD::AND, DL, MVT::i16, Shifted, in LowerSET_ROUNDING()
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/Format/ |
| D | Format.cpp | 2791 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, in fixCppIncludeInsertions() local
2793 Result = Result.merge(tooling::Replacements(Shifted)); in fixCppIncludeInsertions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 5436 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
5437 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false); in createAddRecFromPHI()
5438 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
5446 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted; in createAddRecFromPHI()
5447 return Shifted; in createAddRecFromPHI()
12057 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
12059 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3196 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); in lower() local
3197 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); in lower()
7204 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH() local
7205 MIRBuilder.buildTrunc(Result, Shifted); in lowerSMULH_UMULH()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 5931 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
5933 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 4775 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerGET_ROUNDING() local
4777 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING()
4805 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerSET_ROUNDING() local
4807 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerSET_ROUNDING()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 587 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
6832 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
6843 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
6847 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 12990 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub() local
12992 auto Final = Shifted; in generateEquivalentSub()
12996 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
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| /freebsd-12-stable/contrib/ncurses/misc/ |
| D | terminfo.src | 2575 # Shifted f1-f12 give cons25 codes, rather than xterm function-keys
2859 # Scroll 0-Jump Shifted 3 0-#
8297 # Shifted Function Keys:
11891 # 1= Shifted
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