| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrFMA.td | 323 SchedWriteFMA.Scl>, VEX_LIG;
325 SchedWriteFMA.Scl>, VEX_LIG;
328 SchedWriteFMA.Scl>, VEX_LIG;
330 SchedWriteFMA.Scl>, VEX_LIG;
542 SchedWriteFMA.Scl>,
544 SchedWriteFMA.Scl>;
546 SchedWriteFMA.Scl>,
548 SchedWriteFMA.Scl>;
550 X86any_Fnmadd, loadf32, SchedWriteFMA.Scl>,
552 SchedWriteFMA.Scl>;
[all …]
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| D | X86InstrXOP.td | 78 ssmem, sse_load_f32, SchedWriteFRnd.Scl>;
87 sdmem, sse_load_f64, SchedWriteFRnd.Scl>;
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| D | X86InstrAVX512.td | 2096 SchedWriteFCmp.Scl>, AVX512XSIi8Base;
2100 SchedWriteFCmp.Scl>, AVX512XDIi8Base, VEX_W;
2748 sched.Scl, f32x_info, prd>, VEX_LIG,
2751 sched.Scl, f64x_info, prd>, VEX_LIG,
5358 sched.PS.Scl, IsCommutable>,
5360 sched.PS.Scl, IsCommutable>,
5363 sched.PD.Scl, IsCommutable>,
5365 sched.PD.Scl, IsCommutable>,
5373 VecNode, SaeNode, sched.PS.Scl, IsCommutable,
5377 VecNode, SaeNode, sched.PD.Scl, IsCommutable,
[all …]
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| D | X86Schedule.td | 82 X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.
116 X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.
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| D | X86InstrSSE.td | 1820 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>,
1825 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>,
1832 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, XS;
1836 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, XD;
2625 OpNode, FR32, f32mem, SSEPackedSingle, sched.PS.Scl, 0>,
2628 OpNode, FR64, f64mem, SSEPackedDouble, sched.PD.Scl, 0>,
2634 sched.PS.Scl>, XS;
2637 sched.PD.Scl>, XD;
2648 SSEPackedSingle, sched.PS.Scl, 0>, XS, VEX_4V, VEX_LIG, VEX_WIG;
2651 SSEPackedDouble, sched.PD.Scl, 0>, XD, VEX_4V, VEX_LIG, VEX_WIG;
[all …]
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| D | X86ISelLowering.cpp | 7679 SDValue Scl = N.getOperand(Opcode == ISD::SCALAR_TO_VECTOR ? 0 : 1); in getFauxShuffleMask() local
7690 if (X86::isZeroNode(Scl)) { in getFauxShuffleMask()
7701 unsigned MinBitsPerElt = Scl.getScalarValueSizeInBits(); in getFauxShuffleMask()
7702 while (Scl.getOpcode() == ISD::TRUNCATE || in getFauxShuffleMask()
7703 Scl.getOpcode() == ISD::ANY_EXTEND || in getFauxShuffleMask()
7704 Scl.getOpcode() == ISD::ZERO_EXTEND) { in getFauxShuffleMask()
7705 Scl = Scl.getOperand(0); in getFauxShuffleMask()
7707 std::min<unsigned>(MinBitsPerElt, Scl.getScalarValueSizeInBits()); in getFauxShuffleMask()
7714 if ((Scl.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in getFauxShuffleMask()
7715 Scl.getOpcode() == X86ISD::PEXTRW || in getFauxShuffleMask()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 138 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC in runOnMachineFunction() local
144 OutStreamer->EmitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 160 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC in runOnMachineFunction() local
165 OutStreamer->EmitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 998 SDValue Scl = Op.getOperand(1); in SimplifyDemandedBits() local
1015 unsigned NumSclBits = Scl.getScalarValueSizeInBits(); in SimplifyDemandedBits()
1017 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) in SimplifyDemandedBits()
2658 SDValue Scl = Op.getOperand(1); in SimplifyDemandedVectorElts() local
2674 KnownUndef.setBitVal(Idx, Scl.isUndef()); in SimplifyDemandedVectorElts()
2676 KnownZero.setBitVal(Idx, isNullConstant(Scl) || isNullFPConstant(Scl)); in SimplifyDemandedVectorElts()
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| D | SelectionDAG.cpp | 2514 SDValue Scl; in isSplatValue() local
2523 if (Scl && Scl != Op) in isSplatValue()
2525 Scl = Op; in isSplatValue()
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| /freebsd-12-stable/contrib/binutils/gas/doc/ |
| D | as.texinfo | 3889 * Scl:: @code{.scl @var{class}}
5510 @node Scl
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