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Searched refs:SchedRead (Results 1 – 19 of 19) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVSchedule.td109 def ReadJmp : SchedRead;
110 def ReadJalr : SchedRead;
111 def ReadCSR : SchedRead;
112 def ReadMemBase : SchedRead;
113 def ReadFMemBase : SchedRead;
114 def ReadStoreData : SchedRead;
115 def ReadIALU : SchedRead;
116 def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
117 def ReadShiftImm : SchedRead;
118 def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix
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DRISCVScheduleV.td259 def ReadVLDX : SchedRead;
260 def ReadVSTX : SchedRead;
262 def ReadVSTE8V : SchedRead;
263 def ReadVSTE16V : SchedRead;
264 def ReadVSTE32V : SchedRead;
265 def ReadVSTE64V : SchedRead;
267 def ReadVSTM : SchedRead;
269 def ReadVLDSX : SchedRead;
270 def ReadVSTSX : SchedRead;
271 def ReadVSTS8V : SchedRead;
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DRISCVScheduleB.td32 def ReadSHXADD : SchedRead; // sh1add/sh2add/sh3add
33 def ReadSHXADD32 : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw
36 def ReadRotateImm : SchedRead;
37 def ReadRotateImm32 : SchedRead;
38 def ReadRotateReg : SchedRead;
39 def ReadRotateReg32 : SchedRead;
40 def ReadCLZ : SchedRead;
41 def ReadCLZ32 : SchedRead;
42 def ReadCTZ : SchedRead;
43 def ReadCTZ32 : SchedRead;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64Schedule.td27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
35 def ReadID : SchedRead; // 32/64-bit Divide
38 def ReadIM : SchedRead; // 32/64-bit Multiply
39 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
50 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
86 def ReadVLD : SchedRead;
DAArch64SchedThunderX.td189 // Subtarget-specific SchedRead types.
DAArch64SchedA53.td147 // Subtarget-specific SchedRead types.
DAArch64SchedA55.td180 // Subtarget-specific SchedRead types.
DAArch64SchedCyclone.td862 // Unused SchedRead types
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSchedule.td213 // listed for implicit def operands. SchedRead types may optionally
219 // single SchedWrite and single SchedRead in any order.
229 class SchedRead : SchedReadWrite;
326 // A processor may define a ReadAdvance associated with a SchedRead
336 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
338 SchedRead ReadType = read;
341 // Directly associate a new SchedRead type with a delay and optional
343 class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
346 // Define SchedRead defaults. Reads seldom need special treatment.
347 def ReadDefault : SchedRead;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMSchedule.td61 def ReadALU : SchedRead;
67 def ReadALUsr : SchedRead; // Some operands are read later.
79 def ReadMUL : SchedRead;
86 def ReadMAC : SchedRead;
118 def ReadFPMUL : SchedRead; // multiplier read
119 def ReadFPMAC : SchedRead; // accumulator read
DARMScheduleR52.td9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.
46 def R52Read_ISS : SchedRead;
47 def R52Read_EX1 : SchedRead;
48 def R52Read_EX2 : SchedRead;
49 def R52Read_WRI : SchedRead;
50 def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe
51 def R52Read_F1 : SchedRead;
52 def R52Read_F2 : SchedRead;
DARMScheduleM4.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
DARMScheduleM7.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
DARMScheduleA57.td775 // def A57ReadVFMA : SchedRead;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86Schedule.td15 def ReadAfterLd : SchedRead;
16 def ReadAfterVecLd : SchedRead;
17 def ReadAfterVecXLd : SchedRead;
18 def ReadAfterVecYLd : SchedRead;
22 // This SchedRead describes a bypass delay caused by data being moved from the
24 def ReadInt2Fpu : SchedRead;
48 // The SchedRead to tag register operands than don't need to be ready
50 SchedRead ReadAfterFold;
54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
DX86InstrSSE.td817 SchedRead Int2Fpu = ReadDefault> {
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DSubtargetEmitter.cpp109 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
880 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, in FindReadAdvance() argument
883 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
884 return SchedRead.TheDef; in FindReadAdvance()
888 for (Record *A : SchedRead.Aliases) { in FindReadAdvance()
911 || SchedRead.TheDef == RA->getValueAsDef("ReadType")) { in FindReadAdvance()
922 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { in FindReadAdvance()
925 SchedRead.TheDef->getName()); in FindReadAdvance()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZSchedule.td35 def RegReadAdv : SchedRead;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSISchedule.td27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;