| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 37 SRA = 0x37, enumerator
96 case SRA: in lanaiAluCodeToString()
114 .Case("sha", SRA) in stringToLanaiAluCode()
138 case ISD::SRA: in isdToLanaiAluCode()
139 return AluCode::SRA; in isdToLanaiAluCode()
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| D | LanaiMemAluCombiner.cpp | 224 return LPAC::SRA; in mergedAluCode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
333 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
334 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
335 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. in getArithmeticInstrCost()
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| /freebsd-12-stable/contrib/telnet/libtelnet/ |
| D | auth-proto.h | 98 #ifdef SRA
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| D | auth.c | 168 #ifdef SRA
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| D | sra.c | 35 #ifdef SRA
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| /freebsd-12-stable/crypto/heimdal/appl/telnet/libtelnet/ |
| D | auth-proto.h | 91 #ifdef SRA
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| D | auth.c | 119 #ifdef SRA
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 187 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
189 return SRA; in addIPMSequence()
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| D | SystemZISelDAGToDAG.cpp | 911 case ISD::SRA: { in expandRxSBG()
921 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG()
1904 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean()
1923 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, in expandSelectBoolean()
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| D | SystemZShortenInst.cpp | 370 TwoOperandOpcode == SystemZ::SRA) { in processBlock()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 91 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
815 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
881 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
989 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1161 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
1528 case ISD::SRA: in PromoteIntegerOperand()
2203 case ISD::SRA: in ExpandIntegerResult()
2349 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
2351 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2354 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
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| D | LegalizeVectorOps.cpp | 383 case ISD::SRA: in LegalizeOp()
977 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
989 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
1045 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1373 if (Opc == ISD::SRA) in PromoteIntShiftOp()
1652 case ISD::SRA: return visitSRA(N); in visit()
1779 case ISD::SRA: in combine()
2240 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL; in foldAddSubOfSignBit()
3294 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3297 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3529 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
3584 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt); in visitSUB() local
3585 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA); in visitSUB()
4235 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, in visitSDIVLike()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
78 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
343 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
982 case ISD::SRA: in LowerShifts()
986 Victim = (Opc == ISD::SRA) in LowerShifts()
1204 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 82 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
85 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
306 case ISD::SRA: in LowerShifts()
316 case ISD::SRA: in LowerShifts()
362 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { in LowerShifts()
396 case ISD::SRA: in LowerShifts()
801 case ISD::SRA: in LowerOperation()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 658 SRA, enumerator
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 245 case LPAC::SRA: in getRrMemoryOpValue()
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| /freebsd-12-stable/contrib/gcc/ |
| D | timevar.def | 86 DEFTIMEVAR (TV_TREE_SRA , "tree SRA")
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 101 setOperationAction(ISD::SRA, MVT::i32, Legal); in ARCTargetLowering()
191 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS, in LowerSIGN_EXTEND_INREG()
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1916 for (Record *SRA : SRADefs) { in collectProcResources()
1917 if (SRA->getValueInit("SchedModel")->isComplete()) { in collectProcResources()
1918 Record *ModelDef = SRA->getValueAsDef("SchedModel"); in collectProcResources()
1919 addReadAdvance(SRA, getProcModel(ModelDef).Index); in collectProcResources()
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| /freebsd-12-stable/contrib/gcc/config/s390/ |
| D | s390-modes.def | 52 SRAG, SRA, SRDA)
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicCmpSwapSubword()
561 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicBinOpSubword()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 471 setOperationAction(ISD::SRA, VT, Expand); in AMDGPUTargetLowering()
597 setTargetDAGCombine(ISD::SRA); in AMDGPUTargetLowering()
1744 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
2238 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2482 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
2665 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
3230 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3240 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3352 Src.getOpcode() == ISD::SRA || in performTruncateCombine()
4088 case ISD::SRA: { in PerformDAGCombine()
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