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Searched refs:SLOT2 (Results 1 – 16 of 16) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td206 InstrItinData <tc_01d44cb2, [InstrStage<1, [SLOT2, SLOT3]>]>,
207 InstrItinData <tc_01e1be3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
208 InstrItinData <tc_02fe1c65, [InstrStage<1, [SLOT2, SLOT3]>]>,
211 InstrItinData <tc_0a195f2c, [InstrStage<1, [SLOT2, SLOT3]>]>,
213 InstrItinData <tc_0ba0d5da, [InstrStage<1, [SLOT2]>]>,
214 InstrItinData <tc_0dfac0a7, [InstrStage<1, [SLOT2, SLOT3]>]>,
216 InstrItinData <tc_112d30d6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
220 InstrItinData <tc_151bf368, [InstrStage<1, [SLOT2, SLOT3]>]>,
224 InstrItinData <tc_1c2c7a4a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
226 InstrItinData <tc_1d41f8b7, [InstrStage<1, [SLOT2, SLOT3]>]>,
[all …]
DHexagonDepIICHVX.td108 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
118 [InstrStage<1, [SLOT2, SLOT3], 0>,
123 [InstrStage<1, [SLOT2, SLOT3], 0>,
128 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
140 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
145 [InstrStage<1, [SLOT2, SLOT3], 0>,
151 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
162 [InstrStage<1, [SLOT2, SLOT3], 0>,
178 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
32 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV67T.td11 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
13 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
14 InstrStage<1, [SLOT2, SLOT3]>],
44 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
DHexagonScheduleV60.td20 // | SLOT2 | XTYPE ALU32 J JR |
64 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV62.td20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
DHexagonScheduleV67.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV68.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV66.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonSchedule.td15 def SLOT2 : FuncUnit;
/freebsd-12-stable/contrib/binutils/opcodes/
Dia64-opc.h39 #define SLOT2 IA64_OPCODE_SLOT2 macro
Dia64-opc-b.c312 B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL
364 B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL
366 B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL