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Searched refs:SImode (Results 1 – 25 of 70) sorted by relevance

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/freebsd-12-stable/contrib/gcc/config/
Dgofast.h73 set_conv_libfunc (sfix_optab, SImode, SFmode, "fptosi"); in gofast_maybe_init_libfuncs()
74 set_conv_libfunc (sfix_optab, SImode, DFmode, "dptoli"); in gofast_maybe_init_libfuncs()
75 set_conv_libfunc (ufix_optab, SImode, SFmode, "fptoui"); in gofast_maybe_init_libfuncs()
76 set_conv_libfunc (ufix_optab, SImode, DFmode, "dptoul"); in gofast_maybe_init_libfuncs()
78 set_conv_libfunc (sfloat_optab, SFmode, SImode, "sitofp"); in gofast_maybe_init_libfuncs()
79 set_conv_libfunc (sfloat_optab, DFmode, SImode, "litodp"); in gofast_maybe_init_libfuncs()
/freebsd-12-stable/contrib/gcc/config/sparc/
Dsparc.c968 if (GET_CODE (operands[1]) == LABEL_REF && mode == SImode) in sparc_expand_move()
1039 case SImode: in sparc_expand_move()
2312 case SImode: in emit_soft_tfmode_cvt()
2326 case SImode: in emit_soft_tfmode_cvt()
2340 case SImode: in emit_soft_tfmode_cvt()
2354 case SImode: in emit_soft_tfmode_cvt()
2506 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); in eligible_for_restore_insn()
2531 && register_operand (XEXP (src, 0), SImode) in eligible_for_restore_insn()
2532 && arith_operand (XEXP (src, 1), SImode)) in eligible_for_restore_insn()
2544 && ((register_operand (XEXP (src, 0), SImode) in eligible_for_restore_insn()
[all …]
Dsparc.md349 operands[0] = force_reg (SImode, operands[0]);
516 { operands[3] = gen_reg_rtx (SImode); })
535 { operands[3] = gen_reg_rtx (SImode); })
572 { operands[3] = gen_reg_rtx (SImode); })
582 { operands[3] = gen_reg_rtx (SImode); })
584 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
585 ;; However, the code handles both SImode and DImode.
591 if (GET_MODE (sparc_compare_op0) == SImode)
595 if (GET_MODE (operands[0]) == SImode)
612 else if (GET_MODE (operands[0]) == SImode)
[all …]
Dsparc.h1074 && (FROM) == SImode \
1235 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1239 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
2035 && GET_MODE (X) == SImode \
2058 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2063 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2103 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2273 if (CASE_VECTOR_MODE == SImode) \
2288 if (CASE_VECTOR_MODE == SImode) \
Dpredicates.md222 (ior (match_test "register_operand (op, SImode)")
306 m1 = trunc_int_for_mode (INTVAL (op), SImode);
307 m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode);
331 ;; signed 10-bit immediate field. This is an acceptable SImode operand for
339 ;; signed 11-bit immediate field. This is an acceptable SImode operand for
363 && ((mode == SImode
Dsysv4.h88 do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \
Dsync.md99 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
161 operands[2] = force_reg (SImode, operands[2]);
/freebsd-12-stable/contrib/gcc/config/arm/
Darm.c790 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); in arm_init_libfuncs()
791 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); in arm_init_libfuncs()
794 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); in arm_init_libfuncs()
795 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); in arm_init_libfuncs()
804 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); in arm_init_libfuncs()
805 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); in arm_init_libfuncs()
808 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); in arm_init_libfuncs()
809 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); in arm_init_libfuncs()
824 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); in arm_init_libfuncs()
825 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); in arm_init_libfuncs()
[all …]
Darm.md374 operands[1] = force_reg (SImode, operands[1]);
376 operands[2] = force_reg (SImode, operands[2]);
408 operands[3] = gen_highpart (SImode, operands[0]);
409 operands[0] = gen_lowpart (SImode, operands[0]);
410 operands[4] = gen_highpart (SImode, operands[1]);
411 operands[1] = gen_lowpart (SImode, operands[1]);
412 operands[5] = gen_highpart (SImode, operands[2]);
413 operands[2] = gen_lowpart (SImode, operands[2]);
438 operands[3] = gen_highpart (SImode, operands[0]);
439 operands[0] = gen_lowpart (SImode, operands[0]);
[all …]
Dvfp.md120 ;; SImode moves
127 && ( s_register_operand (operands[0], SImode)
128 || s_register_operand (operands[1], SImode))"
341 operands[0] = gen_highpart (SImode, operands[0]);
342 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
348 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
350 in_lo = gen_lowpart (SImode, operands[1]);
351 out_hi = gen_highpart (SImode, operands[0]);
352 out_lo = gen_lowpart (SImode, operands[0]);
356 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
[all …]
Darm.h408 (MODE) = SImode; \
415 (MODE) = SImode; \
804 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
1052 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1150 else if (MODE == SImode \
1693 emit_move_insn (gen_rtx_MEM (SImode, \
1697 emit_move_insn (gen_rtx_MEM (SImode, \
2083 #define Pmode SImode
Dlinux-elf.h103 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)))
Dpredicates.md315 || GET_MODE (SET_DEST (elt)) != SImode
318 || GET_MODE (SET_SRC (elt)) != SImode
372 || GET_MODE (SET_SRC (elt)) != SImode
375 || GET_MODE (SET_DEST (elt)) != SImode
/freebsd-12-stable/contrib/gcc/config/s390/
Ds390.c734 && GET_MODE (*op0) == SImode in s390_canonicalize_comparison()
1216 wmode = SImode; in s390_expand_logical_operator()
1652 || (GET_MODE (base) != SImode in s390_decompose_address()
1700 || (GET_MODE (indx) != SImode in s390_decompose_address()
2006 return trunc_int_for_mode (value, SImode) == value; in s390_O_constraint_str()
2010 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1; in s390_O_constraint_str()
2014 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1; in s390_O_constraint_str()
2048 part_mode = SImode; in s390_N_constraint_str()
2060 mode = SImode; in s390_N_constraint_str()
2160 case SImode: in s390_rtx_costs()
[all …]
Ds390.md46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
274 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
292 ;; in "RRE" for DImode and "RR" for SImode.
296 ;; to result in "RXY" for DImode and "RX" for SImode.
304 ;; and "lcr" in SImode.
308 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
318 ;; and "cfdbr" in SImode.
322 ;; of a SImode register.
330 ;; in SImode.
[all …]
/freebsd-12-stable/contrib/gcc/config/rs6000/
Drs6000.c2169 tmp = gen_lowpart (SImode, tmp); in const_vector_elt_as_int()
2294 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last)); in gen_easy_altivec_constant()
2614 && mode == SImode in invalid_e500_subreg()
2629 && mode == SImode in invalid_e500_subreg()
2905 || mode != SImode || GET_CODE (x) != MEM) in macho_lo_sum_memory_operand()
3798 case SImode: in rs6000_emit_set_const()
3799 result = no_new_pseudos ? dest : gen_reg_rtx (SImode); in rs6000_emit_set_const()
3805 gen_rtx_IOR (SImode, result, in rs6000_emit_set_const()
3989 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 in rs6000_emit_move()
3991 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 in rs6000_emit_move()
[all …]
Dpredicates.md152 && (mode == SImode || INTVAL (op) < 0x7fff8000))
162 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
164 + (mode == SImode
266 case SImode:
845 || GET_MODE (SET_DEST (elt)) != SImode
848 || GET_MODE (SET_SRC (elt)) != SImode
885 || GET_MODE (SET_SRC (elt)) != SImode
888 || GET_MODE (SET_DEST (elt)) != SImode
1098 || GET_MODE (SET_DEST (exp)) != SImode
1132 || GET_MODE (src_reg) != SImode
[all …]
Dsync.md165 if (<MODE>mode != SImode && <MODE>mode != DImode)
222 if (<MODE>mode != SImode && <MODE>mode != DImode)
265 if (<MODE>mode != SImode && <MODE>mode != DImode)
328 if (<MODE>mode != SImode && <MODE>mode != DImode)
374 if (<MODE>mode != SImode && <MODE>mode != DImode)
440 if (<MODE>mode != SImode && <MODE>mode != DImode)
Drs6000.md149 ; SImode or DImode, even if DImode doesn't fit in GPRs.
583 { operands[1] = gen_lowpart (SImode, operands[1]);
584 operands[2] = gen_reg_rtx (SImode); }")
595 { operands[1] = gen_lowpart (SImode, operands[1]);
596 operands[2] = gen_reg_rtx (SImode); }")
749 { operands[0] = gen_lowpart (SImode, operands[0]);
750 operands[1] = gen_lowpart (SImode, operands[1]);
751 operands[2] = gen_reg_rtx (SImode); }")
762 { operands[0] = gen_lowpart (SImode, operands[0]);
763 operands[1] = gen_lowpart (SImode, operands[1]);
[all …]
/freebsd-12-stable/contrib/gcc/
Dloop-iv.c1577 || GET_MODE (cond) != SImode) in canon_condition()
1578 cond = gen_rtx_fmt_ee (code, SImode, op0, op1); in canon_condition()
1821 cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode, in shorten_into_mode()
1823 cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode, in shorten_into_mode()
2141 assumption = simplify_gen_relational (EQ, SImode, mode, tmp, in iv_number_of_iterations()
2151 assumption = simplify_gen_relational (EQ, SImode, mode, tmp, in iv_number_of_iterations()
2237 may_xform = simplify_gen_relational (cond, SImode, mode, in iv_number_of_iterations()
2240 SImode, mode, in iv_number_of_iterations()
2249 may_xform = simplify_gen_relational (cond, SImode, mode, in iv_number_of_iterations()
2252 SImode, mode, in iv_number_of_iterations()
[all …]
Dcfgloopanal.c517 rtx reg1 = gen_raw_REG (SImode, FIRST_PSEUDO_REGISTER); in init_set_costs()
518 rtx reg2 = gen_raw_REG (SImode, FIRST_PSEUDO_REGISTER + 1); in init_set_costs()
520 rtx mem = validize_mem (gen_rtx_MEM (SImode, addr)); in init_set_costs()
/freebsd-12-stable/contrib/gcc/config/i386/
Di386.c64 : (mode) == SImode ? 2 \
3486 case SImode: in classify_argument()
3738 tmpmode = SImode; in construct_container()
3840 case SImode: in function_arg_advance()
3962 case SImode: in function_arg()
5233 xops[0] = gen_rtx_REG (SImode, regno); in ix86_file_end()
5234 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx); in ix86_file_end()
5797 rtx eax = gen_rtx_REG (SImode, 0); in ix86_expand_prologue()
5827 emit_move_insn (eax, gen_rtx_MEM (SImode, t)); in ix86_expand_prologue()
5889 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode)) in ix86_emit_restore_regs_using_mov()
[all …]
Dpredicates.md69 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
106 return trunc_int_for_mode (val, SImode) == val;
166 && trunc_int_for_mode (offset, SImode) == offset)
174 && trunc_int_for_mode (offset, SImode) == offset)
183 && trunc_int_for_mode (offset, SImode) == offset)
187 && trunc_int_for_mode (offset, SImode) == offset)
197 && trunc_int_for_mode (offset, SImode) == offset)
271 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
285 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
962 ;; Modern CPUs have same latency for HImode and SImode multiply,
Di386.h927 || (MODE) == V2SImode || (MODE) == SImode)
938 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
976 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
977 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1785 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1843 (MODE) = SImode; \
1849 #define Pmode (TARGET_64BIT ? DImode : SImode)
Di386.md47 ;; 'k' Likewise, print the SImode name of the register.
537 operands[0] = force_reg (SImode, operands[0]);
1096 "ix86_expand_move (SImode, operands); DONE;")
1483 ;; Situation is quite tricky about when to choose full sized (SImode) move
1888 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1903 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
3062 ; zero extend to SImode here to avoid partial register stalls
4113 ;; Signed conversion to SImode.
4142 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4482 convert_to_mode (SImode, operands[1], 0)));
[all …]

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