| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1365 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) enumerator
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelDAGToDAG.cpp | 81 case ISD::SETUO: in fpCondCode2Fcc()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 200 case FCmpInst::FCMP_UNO: return ISD::SETUO; in getFCmpCondCode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 448 case ISD::SETUO: return "setuo"; in getOperationName()
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| D | TargetLowering.cpp | 350 case ISD::SETUO: in softenSetCCOperands()
4192 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
4242 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
8727 ISD::CondCode::SETUO); in expandFP_TO_INT_SAT()
8756 return DAG.getSelectCC(dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); in expandFP_TO_INT_SAT()
8876 case ISD::SETUO: in LegalizeSetCCCondCode()
8900 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; in LegalizeSetCCCondCode()
8925 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; in LegalizeSetCCCondCode()
8944 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { in LegalizeSetCCCondCode()
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| D | SelectionDAG.cpp | 540 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT in getSetCCAndOperation()
2236 case ISD::SETUO: in FoldSetCC()
2325 case ISD::SETUO: return getBoolConstant(R==APFloat::cmpUnordered, dl, VT, in FoldSetCC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 274 def COND_UO : PatFrags<(ops), [(OtherVT SETUO)]>;
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| D | SIWholeQuadMode.cpp | 824 case ISD::SETUO: in lowerKillF32()
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| D | R600ISelLowering.cpp | 99 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 1456 case ISD::SETUO: in combineFMinMaxLegacy()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 726 def SETUO : CondCode<"FCMP_UNO">;
1329 (setcc node:$lhs, node:$rhs, SETUO)>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 859 case ISD::SETUO: in IntCondCCodeToICC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 1276 defm FCMUO_PPzZZ : sve_fp_3op_p_pd_cc<0b100, "fcmuo", SETUO, SETUO, SETUO, SETUO>;
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| D | AArch64ISelLowering.cpp | 2361 case ISD::SETUO: in changeFPCCToAArch64CC()
2432 case ISD::SETUO: in changeVectorFPCCToAArch64CC()
14514 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 115 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4130 case ISD::SETUO: return PPC::PRED_UN; in getPredicateForSetCC()
4150 case ISD::SETUO: return 3; // Bit #3 = SETUO in getCRIdxForSetCC()
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| D | PPCISelLowering.cpp | 617 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in PPCTargetLowering()
618 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); in PPCTargetLowering()
940 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
993 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 557 case ISD::SETUO: in getPTXCmpMode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 140 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
141 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
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| D | MipsSEISelLowering.cpp | 1859 Op->getOperand(2), ISD::SETUO); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 620 case ISD::SETUO: return Mips::FCOND_UN; in condCodeToFCC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1401 case ISD::SETUO: return SPCC::FCC_U; in FPCondCCodeToFCC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2098 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO; in CCMaskForCondCode()
2902 case ISD::SETUO: in lowerVectorSETCC()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 305 ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; in RISCVTargetLowering()
581 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, in RISCVTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5096 case ISD::SETUO: return X86::COND_P; in TranslateX86CC()
21776 dl, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO); in LowerFP_TO_INT_SAT()
21815 dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); in LowerFP_TO_INT_SAT()
22861 case ISD::SETUO: SSECC = 3; break; in translateX86FSETCC()
22886 case ISD::SETUO: in translateX86FSETCC()
47763 SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType, Op0, Op0, ISD::SETUO); in combineFMinNumFMaxNum()
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