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Searched refs:SETULT (Results 1 – 25 of 50) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1369 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1395 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVEISelDAGToDAG.cpp43 case ISD::SETULT: in intCondCode2Icc()
87 case ISD::SETULT: in fpCondCode2Fcc()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DAnalysis.cpp204 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
216 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
236 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3297 case ISD::SETULT: { in get32BitZExtCompare()
3470 case ISD::SETULT: { in get32BitSExtCompare()
3626 case ISD::SETULT: { in get64BitZExtCompare()
3789 case ISD::SETULT: { in get64BitSExtCompare()
4044 case ISD::SETULT: in SelectCC()
4071 case ISD::SETULT: in SelectCC()
4132 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4164 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4186 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4194 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
DPPCInstrInfo.td3740 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3803 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3983 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
4011 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
4023 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
4051 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
4246 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
4277 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
4298 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
4320 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
DPPCInstrSPE.td840 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp581 case ISD::SETULT: in NegateCC()
793 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
DBPFInstrInfo.td101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
DWebAssemblyISelLowering.cpp116 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
236 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp371 case ISD::SETULT: in softenSetCCOperands()
3260 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3461 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
3463 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
3465 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
3468 unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); in simplifySetCCWithCTPOP()
3476 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
3738 case ISD::SETULT: in SimplifySetCC()
3761 case ISD::SETULT: in SimplifySetCC()
3954 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp1625 case ISD::SETULT: in PromoteSetCCOperands()
2481 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2551 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
2681 ISD::SETULT); in ExpandIntRes_ADDSUB()
2693 ISD::SETULT); in ExpandIntRes_ADDSUB()
2702 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2775 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3613 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
4335 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
4405 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp452 case ISD::SETULT: return "setult"; in getOperationName()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVVLPatterns.td743 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
750 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
754 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
764 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT,
DRISCVInstrInfoVSDPatterns.td452 defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
455 defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCISelLowering.cpp48 case ISD::SETULT: in ISDCCtoARCCC()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td284 def COND_ULT : PatFrag<(ops), (OtherVT SETULT)>;
DR600ISelLowering.cpp108 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
114 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
DSIWholeQuadMode.cpp812 case ISD::SETULT: in lowerKillF32()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp960 case ISD::SETULT: in isLegalDSPCondCode()
1766 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1772 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1855 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
DMipsDSPInstrInfo.td1428 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1441 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp519 case ISD::SETULT: in intCCToAVRCC()
643 CC = ISD::SETULT; in getAVRCmp()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/
DM68kISelLowering.cpp1497 case ISD::SETULT: in TranslateIntegerM68kCC()
1575 case ISD::SETULT: in TranslateM68kCC()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td730 def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
1337 (setcc node:$lhs, node:$rhs, SETULT)>;

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