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Searched refs:SETLT (Results 1 – 25 of 52) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1378 SETLT, // 1 X 1 0 0 True if less than enumerator
1389 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVEISelDAGToDAG.cpp35 case ISD::SETLT: in intCondCode2Icc()
67 case ISD::SETLT: in fpCondCode2Fcc()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp583 case ISD::SETLT: in NegateCC()
792 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
803 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
DBPFInstrInfo.td99 [{return (N->getZExtValue() == ISD::SETLT);}]>;
119 [{return (N->getZExtValue() == ISD::SETLT);}]>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DAnalysis.cpp216 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
235 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
DTargetLoweringBase.cpp675 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
676 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
677 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
678 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3243 case ISD::SETLT: { in get32BitZExtCompare()
3422 case ISD::SETLT: { in get32BitSExtCompare()
3577 case ISD::SETLT: { in get64BitZExtCompare()
3737 case ISD::SETLT: { in get64BitSExtCompare()
4040 case ISD::SETLT: in SelectCC()
4067 case ISD::SETLT: in SelectCC()
4118 case ISD::SETLT: in getPredicateForSetCC()
4145 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
4182 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
4228 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
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DPPCInstrInfo.td3738 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3878 defm : ExtSetCCPat<SETLT,
3910 defm : ExtSetCCPat<SETLT,
3985 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
4013 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
4025 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
4053 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
4140 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
4184 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
4211 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
DPPCInstrSPE.td838 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
859 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp329 case ISD::SETLT: in softenSetCCOperands()
777 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyMultipleUseDemandedBits()
1419 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyDemandedBits()
3746 case ISD::SETLT: in SimplifySetCC()
3954 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
3966 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
4081 ISD::SETLT); in SimplifySetCC()
4371 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
6003 return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); in getSqrtInputTest()
6451 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT); in expandMUL_LOHI()
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DLegalizeIntegerTypes.cpp1631 case ISD::SETLT: in PromoteSetCCOperands()
2549 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3470 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT); in ExpandIntRes_MULFIX()
3611 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
3620 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT); in ExpandIntRes_MULFIX()
3624 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
3638 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); in ExpandIntRes_MULFIX()
3733 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT); in ExpandIntRes_SADDSUBO()
4323 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
4334 case ISD::SETLT: in IntegerExpandSetCCOperands()
[all …]
DSelectionDAGDumper.cpp459 case ISD::SETLT: return "setlt"; in getOperationName()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1008 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1025 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1033 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1080 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td271 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
297 def COND_SLT : PatFrag<(ops), (OtherVT SETLT)>;
DAMDGPUISelLowering.cpp1468 case ISD::SETLT: { in combineFMinMaxLegacy()
2125 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2126 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2247 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2784 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT); in LowerFP_TO_FP16()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVVLPatterns.td742 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
749 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
753 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
762 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT,
1079 defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
DRISCVInstrInfoVSDPatterns.td451 defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
453 defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
704 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp515 case ISD::SETLT: in intCCToAVRCC()
587 CC = ISD::SETLT; in getAVRCmp()
602 CC = ISD::SETLT; in getAVRCmp()
605 case ISD::SETLT: { in getAVRCmp()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
1108 case ISD::SETLT: in EmitCMP()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/
DM68kISelLowering.cpp1491 case ISD::SETLT: in TranslateIntegerM68kCC()
1521 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateM68kCC()
1525 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1576 case ISD::SETLT: in TranslateM68kCC()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCISelLowering.cpp60 case ISD::SETLT: in ISDCCtoARCCC()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
123 def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
170 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
171 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
172 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
173 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
DMipsDSPInstrInfo.td1422 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1435 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1246 defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt", SETGT, SETLT>;
1262 defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt", SETGT, SETLT>;
1263 defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, SETGT>;
1273 defm FCMGT_PPzZZ : sve_fp_3op_p_pd_cc<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>;
1281 defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>;
1282 defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt", SETOLT, SETLT, SETOGT, SETGT>;

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