Home
last modified time | relevance | path

Searched refs:SCALAR_TO_VECTOR (Results 1 – 20 of 20) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h583 SCALAR_TO_VECTOR, enumerator
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
281 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
704 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
721 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_UnaryOp_StrictFP()
787 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); in ScalarizeVecOp_VSETCC()
818 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_FP_ROUND()
833 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
847 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_FP_EXTEND()
862 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_EXTEND()
929 case ISD::SCALAR_TO_VECTOR: in SplitVectorResult()
[all …]
DLegalizeDAG.cpp407 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1789 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
1897 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
1952 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
1955 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
2977 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
4876 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
DSelectionDAGDumper.cpp291 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
DLegalizeIntegerTypes.cpp112 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
1499 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
4252 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
4842 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); in PromoteIntRes_SCALAR_TO_VECTOR()
DDAGCombiner.cpp1718 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
4907 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && in hoistLogicOpWithSameOpcodeHands()
18722 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
18789 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
18933 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
20016 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
20050 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar); in visitCONCAT_VECTORS()
20759 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
21193 SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); in visitVECTOR_SHUFFLE()
21642 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Val); in visitSCALAR_TO_VECTOR()
DSelectionDAG.cpp2908 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
5020 case ISD::SCALAR_TO_VECTOR: in getNode()
DTargetLowering.cpp959 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedBits()
2422 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedVectorElts()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp989 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
1425 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
1735 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
2009 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR); in X86TargetLowering()
2766 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
3006 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned); in lowerRegToMasks()
3346 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val) in LowerMemArgument()
4100 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); in LowerCall()
6737 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetConstantBitsFromNode()
7433 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetShuffleAndZeroables()
[all …]
DX86ISelDAGToDAG.cpp1126 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1128 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
DX86FastISel.cpp2645 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp491 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
751 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in SelectBuildVector()
824 case ISD::SCALAR_TO_VECTOR: in Select()
3160 case ISD::SCALAR_TO_VECTOR: in Select()
DSIISelLowering.cpp283 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
313 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
314 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
327 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
328 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32); in SITargetLowering()
341 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
342 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32); in SITargetLowering()
355 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
356 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32); in SITargetLowering()
369 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp378 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
494 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
495 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
4943 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
5206 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
5230 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
5402 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
5518 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp824 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
932 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
949 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
953 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
954 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
955 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
956 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
2920 UI->getOpcode() != ISD::SCALAR_TO_VECTOR && in usePartialVectorLoads()
[all …]
DPPCISelDAGToDAG.cpp5523 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR && in Select()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td671 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in addMVEVectorTypes()
391 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in addMVEVectorTypes()
437 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in addMVEVectorTypes()
5901 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
5903 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
7758 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
8540 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerVECTOR_SHUFFLE()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp4696 SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load); in LowerLOAD()
9367 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) in LowerVECTOR_SHUFFLE()
10153 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
10354 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); in LowerBUILD_VECTOR()
16007 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); in performSelectCombine()
16009 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); in performSelectCombine()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1649 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()